Power-Gating Scheme and Modeling of Near-Threshold Adiabatic Flip-Flops

Abstract

Technology scaling increases the density and performance of nanometer circuits, resulting in both large dynamic and leakage dissipations. This paper presents power-gating scheme, modeling, and o ptimization of adiabatic flip-flops operating on n ear-threshold regions to reduce both dynamic and leakage dissipations. The power-gated logic blocks are realized with c omplementary pass-transistor adiabatic logic with the dual threshold technique to reduce active leakage dissipations. The improved c omplementary pass-transistor adiabatic logic circuits are used as the two-phase power-gating switches to reduce the sleep leakage dissipations. The analytical model for power-gating adiabatic sequential circuits was constructed, and the energy overhead of the proposed power-gating scheme was analyzed in detail. Near-threshold computing for a power-gating adiabatic mode-10 counter was verified. The results show that the proposed power-gating technique is suitable for the adiabatic units operating on near-threshold region s . DOI : http://dx.doi.org/10.11591/telkomnika.v12i1.3378