Reliable Power Gating With NBTI Aging Benefits

Abstract

In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for power-gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32-nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test chip manufactured with a 65-nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower $V_{\textrm {th}}$ compared with the standard STs. This can be achieved by either redesigning the STs with the identified $V_{\textrm {th}}$ value or applying a proper forward body bias to the available power switching fabrics. Through the HSPICE simulations, we show LT extension up to $21.4\times $ and average static power reduction up to 16.3% compared with the standard ST design approach, without additional area overhead. Finally, we show LT extension and several performance-cost tradeoffs when a target maximum LT is considered.