Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology

Abstract

Reliability of advanced deeply scaled CMOS technologies is being threatened by time-dependent degradation mechanisms such as Negative Bias Temperature Instability (NBTI) phenomenon that cause workload-dependent shifts on a transistor's threshold voltage (Vth), and performance during its lifetime. In this study, NBTI related performance degradation of datapath logic subblocks (i.e. adder, multiplier, shifter, mux-demux) are investigated in relation to workload dependency, and architectural topology at 10nm FinFET technology. A workload-dependent, NBTI aging-aware digital design flow was developed within the industry standard EDA tool chain. NBTI model is based on the measured Capture and Emission Time (CET) maps, and scaled to 10nm node. Static Timing Analysis (STA) is performed to evaluate the performance degradation at 3σ corner. Results on datapath subblocks under NBTI aging after 3 years show a performance loss up to 16.7%. NBTI aging results in the replacement of the time-zero critical path by a non-critical path during a circuit's lifetime, and it can be significantly high as 91%. Finally, the correlation between aging sensitivity to workload variations, and architectural parameters are shown, and it can vary 12×, and 9×, respectively.