Power Efficient Architecture Research Articles

Design and implementation of power and area efficient architectures of circular symmetry 2-D FIR filters using CSOA-based CSD

Design and implementation of power and area efficient architectures of circular symmetry 2-D FIR filters using CSOA-based CSD

Survey on Power and Area efficient FIR Filter Architecture in Digital Encephalography System

In the process of Electroencephalogram (EEG) acquisition, the electrical signals from the brain are contaminated by numerous noise sources and artifacts. American Clinical Neurophysiology Society recommends digital filtering of acquired EEG signals with an upper cut-off frequency of 70 Hz before display in digital encephalography systems. We propose a linear symmetrical FIR filter architecture for filtering EEG signals using approximate computation techniques. Approximate computation techniques result in lower hardware resources and lower power consumption with some compromise in quality. Software tools used for this study include MATLAB (and its FDA tool) and Xilinx ISE 14.7. The chosen target platform is the Spartan-3e starter FPGA board. We propose the architecture for an Approximate Dadda Tree Multiplier. The proposed approximate multiplier consumes 25% lesser slices and 35.18% lower dynamic power than state-of-the-art approximate multipliers. The proposed FIR filter consumes 19.77% lesser LUTs and 34.97% lower power than state-of-the-art symmetric FIR filter architectures.

Energy efficient noise error pattern generator for guessing decoding in bursty channels

For the hard guessing random additive noise decoding Markov order (GRAND-MO) algorithm, it is crucial to develop an efficient noise error patterns (NEPs) generator to facilitate its application in bursty channels. This paper proposes a practical hardware realization by generating the NEPs in a sequential manner. Based on classification of the four types of NEPs, we propose to iteratively calculate the “1" and the “0" permutations in the same time. Then, the novel “0" permutation regularization and bit flipping techniques are employed, through which the generation of the four types of NEPs is uniformed at the same way. Moreover, the proposed NEPs generator can generate all NEPs by using the “1" burst parameters, and is suitable for the guessing decoding of any linear block codes. Built on field programmable gate array (FPGA) implementation and comparison with existing benchmark, we show the proposed NEPs generator is a power-efficient architecture for realization. This work presents a new solution for the hardware implementation of the NEPs generator in GRAND-MO.

Area, power efficient Vedic multiplier architecture using novel 4:2 compressor

Area, power efficient Vedic multiplier architecture using novel 4:2 compressor

A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders

Directly or indirectly adders are the basic elements in almost all digital circuits, three operand adders are the basic building blocks in LCG (Linear congruential generator) based pseudo-random bit generators. Elementary adders are fast, area and power efficient for small bit sizes. Carry save adder computes the addition in O(n) time complexity, due to its ripple carry stage. Parallel prefix adders such as Han-Carlson compute the addition in O(log(n)) time complexity but at the cost of additional circuitry. Hence new high-speed power-efficient adder architecture is proposed which uses four stages to compute the addition, which consumes less power, and the adder delay decreases to O(n/2). Even though it is not much faster than the High-speed Area efficient VLSI architecture of three operand adders (HSAT3), it computes the addition by utilizing less power. The proposed architecture is implemented using Verilog HDL in Xilinx 14.7 design environment and it is evident that this adder architecture is 2 times faster than the carry save adder and 1, 1.5, 1.75 times faster than the hybrid adder structure for 32, 64, 128 bits respectively. Also, power utilization is 1.95 times lesser than HSAT3, 1.94 times lesser than the Han-Carlson adder, and achieves the lowest PDP than the existing three operand techniques.

Power and area efficient FIR filter architecture in digital encephalography systems

In the process of Electroencephalogram (EEG) acquisition, the electrical signals from the brain are contaminated by numerous noise sources and artifacts. American Clinical Neurophysiology Society recommends digital filtering of acquired EEG signals with an upper cut-off frequency of 70 Hz before display in digital encephalography systems. We propose a linear symmetrical FIR filter architecture for filtering EEG signals using approximate computation techniques. Approximate computation techniques result in lower hardware resources and lower power consumption with some compromise in quality. Software tools used for this study include MATLAB (and its FDA tool) and Xilinx ISE 14.7. The chosen target platform is the Spartan-3e starter FPGA board. We propose the architecture for an Approximate Dadda Tree Multiplier. The proposed approximate multiplier consumes 25% lesser slices and 35.18% lower dynamic power than state-of-the-art approximate multipliers. The proposed FIR filter consumes 19.77% lesser LUTs and 34.97% lower power than state-of-the-art symmetric FIR filter architectures.

Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

: This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

Design and Implementation of Low Power and Area Efficient Architecture for High Performance ALU

Digital Signal Processors (DSP) have a ubiquitous presence in almost all civil and military signal processing applications, including mission critical environments like nuclear reactors, process control etc. Arithmetic and Logic units (ALU), being the heart of any digital signal processor, play critical and decisive roles in achieving the required parameter benchmarks and the overall efficiency and robustness of the digital signal processor. State of the art research has shown successful traction with the performance requirements of critical Multiply-Accumulate (MAC) parameters, like reduced power consumption, small electronic real estate footprint and reduction in delay with the associated design complexity. Judicious placement of its building blocks, namely, the truncated multiplier and half-sum carry generation-sum carry generation (HSCG-SCG) adder in the architectural design of ALU and the type of adder and multiplier circuits selected are the core decisions that decide the overall performance of the ALU. To overcome the drawback and to improve the performance further, this work proposes a new architecture for the square root (SQRT) carry select adder (CSLA) using half-sum generation (HSG), half-carry generation (HCG), full-sum generation (FSG) and full-carry generation (FCG) blocks. The proposed design contains N-bit architecture, and comparative results are considered for 8-bit, 16-bit and 32-bit combinations. All the designs are implemented in the Xilinx ISE environment and the results show that better area, power, and delay performance compared to the state of art methods.

An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications

The mortality rate due to cardiac abnormalities is enormous, making the development of wearables to monitor functioning of the heart of paramount importance. In this paper, wepresent a resource efficient and low power architecture using Integer Haar Wavelet Transform for the complete delineation of ECG signal. The novelty of the algorithm lies in the use of single scale wavelet coefficients to delineate P-QRS-T features making it computationally simple. The proposed architecture is implemented using Xilinx FPGA ZedBoard Zynq™ −7000 platform, and utilises only 4.38% of the available resources. It is synthesised using 180 nm CMOS technology consuming 0.88 μW power, making it area as well as power-efficient for the wearable IoT healthcare devices.

A 5-pJ/Bit OOK Transmitter Using MEMS-Based RF Oscillator for IoT Application in 180-nm CMOS

An 800-MHz OOK transmitter for short-range Internet-of-Things (IoT) applications is presented in this letter. The OOK transmitter utilizes a microelectromechanical system (MEMS)-based RF oscillator for carrier frequency generation, leading to a hardware- and power-efficient architecture. The transmitter is implemented in a 180-nm CMOS process and delivers −12.4-dBm output power. The power consumption of the MEMS oscillator is only 0.24-mW with 126.3-dBc/Hz phase noise at 100-kHz offset and a figure-of-merit (FoM) of 210.5 dB due to the optimized high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> aluminum nitride (AlN) piezoelectric MEMS resonator. The transmitter can provide a 120-Mb/s data rate of OOK modulation with an energy efficiency of 5 pJ/bit by directly switching ON/OFF the power amplifier (PA). The 175-ns startup time of the MEMS-based oscillator can support very heavy duty-cycle transmitter operation, leading to ultralow average power consumption of 50 nW.

A 24–28-GHz Four-Element Phased-Array Transceiver Front End With 21.1%/16.6% Transmitter Peak/OP1dB PAE and Subdegree Phase Resolution Supporting 2.4 Gb/s in 256-QAM for 5-G Communications

This article presents a power efficient 24-28-GHz four-element phased-array transceiver (TRX) front end (FE) for 5-G base stations and user equipment communications. A power efficient hybrid quadrature vector interpolation-based phase-shifting architecture is proposed to increase the TX and RX power efficiency and phase resolution. A transformer-based embedded T/R switch is proposed which minimizes TX and RX losses to ensure high TX output power and power efficiency while maintaining a low noise figure (NF) and extremely compact chip area. The 24-28-GHz four-element TRX FE is implemented in a 65-nm CMOS process (1P9M) for large-scale phased-array applications. The TX and RX paths achieve 0.8° phase resolution with <; 0.47°/0.17-dB RMS phase/gain error as well as 24-dB gain control range with 0.75-dB gain step and <; 0.1°/0.4-dB RMS gain/phase error over 24-30 GHz. The full TX path (including splitter and T/R switch) also achieves a measured 16.6-/18.9-dBm OP1dB/ P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> with 21.1%/16.6% PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> /OP1dB for each FE element while maintaining a minimum 4.4-dB NF in the full RX path (including combiner, T/R switch, and OFF-mode PA) at 28 GHz. Under the 64-/256-QAM modulation measurements, the full TX path achieves a state-of-the-art average output power of 13.5-/10.2-dBm per element (8.4%/3.5% full TX path PAE) with -26.4/-30.8 dB EVM and 27.8-/30.1-dB ACLR at 28 GHz, making the proposed TRX FE can be effectively deployed in both base stations and user equipment for 5-G communications. The chip size of the four-element TRX FE excluding I/O pads is only 3.4×1.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Realization of an ultra low power and area efficient SC SAR ADC architecture using single and two step reset methods

Realization of an ultra low power and area efficient SC SAR ADC architecture using single and two step reset methods

A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS

A folding voltage-to-time converter (VTC) is proposed for low-power time-based (TB) flash ADCs performing voltage-to-time-to-digital conversion. Conventional VTCs in TB flash ADCs generate multiple time outputs or have nonlinear conversion gain, resulting in a large power consumption in time-to-digital converters (TDCs) due to power-inefficient architectures using a lot of comparators. The proposed VTC generates a single time output with a large-and-linear conversion gain because the proposed VTC folds the whole voltage input range several times and each voltage-to-time conversion is defined within the voltage range reduced by folding. This allows the TDC power consumption to be reduced by using power-efficient architectures. Moreover, the VTC generates digital outputs as a result of the folding operation, thereby relaxing the resolution requirement of the TDC. A 7-bit TB ADC is implemented with a 4× folding VTC having a 2-bit digital output and a 5-bit pipelined TDC for high-speed low-power operation. A TB ADC fabricated in a 1-V 65-nm CMOS process achieves a 4-GS/s sampling frequency, 11.3-mW power consumption, a 34.58-dB SNDR, and a 64.5-fJ/conv.-step figure of merit (FoM).

A TD-ADC for IR-UWB Radars With Equivalent Sampling Technology and 8-GS/s Effective Sampling Rate

A high-speed time domain analog-to-digital converter (ADC) customized for impulse radio ultra-wideband (IR-UWB) radars is proposed in this brief. It adopts a power efficient architecture combining time domain implementation and equivalent sampling technology. The equivalent sampling rate is high up to 8 GS/s. Compared to time interleaved (TI) ADC, the proposed time domain ADC (TD-ADC) not only has less power consumption and silicon area, but also is free from complicated digital calibration. The prototype ADC was fabricated in a 65nm CMOS technology. The achieve area is 320 μm × 300 μm. With the Nyquist middle frequency input of 1.376 GHz, the measured spurious free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) are over 57.6 dB and 43.0 dB, while the real time power consumption is only 8.2 mW. The figure of merit (FOM) is about 147 fJ/step.

A Digital Readout IC for Microbolometer Imagers Offering Low Power and Improved Self-Heating Compensation

This paper presents a novel and power efficient readout architecture for uncooled microbolometers that offers adequate noise performance along with a circuit-based method for self-heating compensation. The proposed method employs an event-generation scheme and a time-mode readout chain to achieve dynamic mode of operation resulting in low power. The readout chain consists of a capacitive transimpedance amplifier (CTIA) based current-to-time converter followed by a two stage time-to-digital converter (TDC). The CTIA employs a novel integration scheme for time amplification along with a modified reset mechanism to achieve self-heating compensation. We also present a model to analyze the implications of time-mode readout on imager operation. An experimental readout chip, based on this approach, has been designed using a 130 nm bulk CMOS technology. The proposed architecture offers robust frontend processing and achieves a per channel power consumption of $66~\mu \text{W}$ , which is considerably lower than the most recently reported designs, while maintaining better than 10-mK readout noise equivalent temperature difference (NETD).

Crowd counting´a la Bourdieu: Automated estimation of the number of people

In recent years, sociologists have taught us how important and emergent the problem of crowd counting is. They have recognised a variety of reasons for this fact, including: public safety (e.g. crushing between people, trampling underfoot, risk of spreading infectious disease, aggression), politics (e.g. police and government tend to underestimate the number of people, whilst protest organisers tend to overestimate it) and journalism (e.g. accuracy of the estimation of the ground truth supporting an article). The aim of this paper is to investigate models for crowd counting that are inspired by the observations of famous sociologist Pierre Bourdieu. We show that despite the simplicity of the models, we can achieve competitive result. This makes them suitable for low computational power and energy efficient architectures.

Area–Time–Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Fast Fourier transform (FFT) is a significant technique in the digital signal processing (DSP). The intrinsic weak point of the primary designs of FFT was the use of multipliers. CORDIC is the most prevalent method to replace the multipliers of FFTs. In order to enhance the speed of CORDIC, redundant binary signed-digit (BSD) encodings can be utilized, so-called BSD-CORDIC. The main goal of this paper is to improve the efficiency of BSD-CORDIC-based FFT. The redundant improved composed (RIC) CORDIC is proposed as a novel BSD-CORDIC. The main idea behind the RIC CORDIC lies in prior determination of the required iterations in such a way that the maximum number of iterations is reduced, which results in speedup and decrease in hardware resources. Also, some of the iterations still can be skipped, which leads to further reduction in the power consumption. The synthesis results demonstrate that the FFT based on the RIC BSD-CORDIC enhances speed, power consumption, and area overhead.

Design Exploration and Performance Strategies towards Power-Efficient FPGA-Based Architectures for Sound Source Localization

Many applications rely on MEMS microphone arrays for locating sound sources prior to their execution. Those applications not only are executed under real-time constraints but also are often embedded on low-power devices. These environments become challenging when increasing the number of microphones or requiring dynamic responses. Field-Programmable Gate Arrays (FPGAs) are usually chosen due to their flexibility and computational power. This work intends to guide the design of reconfigurable acoustic beamforming architectures, which are not only able to accurately determine the sound Direction-Of-Arrival (DoA) but also capable to satisfy the most demanding applications in terms of power efficiency. Design considerations of the required operations performing the sound location are discussed and analysed in order to facilitate the elaboration of reconfigurable acoustic beamforming architectures. Performance strategies are proposed and evaluated based on the characteristics of the presented architecture. This power-efficient architecture is compared to a different architecture prioritizing performance in order to reveal the unavoidable design trade-offs.

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

SummaryViterbi decoder (VD) is the majority used decoder for convolutional codes which play a role in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the metric at each stage to obtain a shortest path from every state to the next state. Existing techniques in VD design are namely (a) pipelined architecture, (b) modular ACS and buffers technique, and (c) quasi cyclic trellis technique. The key challenge of the VD trellis circuit is to attain high throughput and better latency performance with low power consumption without affecting hardware complexity of VD. This paper presents several of conventional methods used in VD. We also proposed a new method for VD with K the constraint length as multiple of M, the radix in trellis to calculate the shortest survival path to travel in trellis. The proposed VD is simulated using Xilinx. Use of a trace back approach in the proposed Viterbi decoder with capacitive and resistive feedback yields better throughput, latency, and power consumption with respect to other techniques. The static power outputs obtained in RE, shift update, and selective update methods using Libero IDE are also compared.

Area and Power Efficient Pipeline FFT Architecture for QPSK-OFDM

Area and Power Efficient Pipeline FFT Architecture for QPSK-OFDM