Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Abstract

SummaryViterbi decoder (VD) is the majority used decoder for convolutional codes which play a role in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the metric at each stage to obtain a shortest path from every state to the next state. Existing techniques in VD design are namely (a) pipelined architecture, (b) modular ACS and buffers technique, and (c) quasi cyclic trellis technique. The key challenge of the VD trellis circuit is to attain high throughput and better latency performance with low power consumption without affecting hardware complexity of VD. This paper presents several of conventional methods used in VD. We also proposed a new method for VD with K the constraint length as multiple of M, the radix in trellis to calculate the shortest survival path to travel in trellis. The proposed VD is simulated using Xilinx. Use of a trace back approach in the proposed Viterbi decoder with capacitive and resistive feedback yields better throughput, latency, and power consumption with respect to other techniques. The static power outputs obtained in RE, shift update, and selective update methods using Libero IDE are also compared.