Survey on Power and Area efficient FIR Filter Architecture in Digital Encephalography System

Abstract

In the process of Electroencephalogram (EEG) acquisition, the electrical signals from the brain are contaminated by numerous noise sources and artifacts. American Clinical Neurophysiology Society recommends digital filtering of acquired EEG signals with an upper cut-off frequency of 70 Hz before display in digital encephalography systems. We propose a linear symmetrical FIR filter architecture for filtering EEG signals using approximate computation techniques. Approximate computation techniques result in lower hardware resources and lower power consumption with some compromise in quality. Software tools used for this study include MATLAB (and its FDA tool) and Xilinx ISE 14.7. The chosen target platform is the Spartan-3e starter FPGA board. We propose the architecture for an Approximate Dadda Tree Multiplier. The proposed approximate multiplier consumes 25% lesser slices and 35.18% lower dynamic power than state-of-the-art approximate multipliers. The proposed FIR filter consumes 19.77% lesser LUTs and 34.97% lower power than state-of-the-art symmetric FIR filter architectures.