Systolic Architecture for High Speed FIR Filter Using VLSI Technology

Monika Dattatraya Wavhal

doi:10.24297/ijct.v14i11.1805

Monika Dattatraya Wavhal

Open Access

https://doi.org/10.24297/ijct.v14i11.1805

Copy DOI

Abstract

The tremendous growth of computer and Internet technology wants the data to be processed athigh speed. Low power consumption, high throughput and optimized hardware are the most important design criteriaâ€™s for VLSI implementation. This project gives an efficient design of high speed FIR filters using systolic architecture. In this paper we have implemented 7th,8th,11th order FIR filter with 8 bit normalized input. To obtain efficient results we have selected B1 design from all the designs of systolic arrays.GF (28) multiplier and XOR adder are used for multiplication and addition in filter. Hamming window technique is used to derive the filter coefficients. The coefficients of filter are found out using Matlab. The FIR filter architecture is effectively synthesized and simulated using Xilinx ISE 8.1i in VHDL and Modelsim simulator. Maximum frequency, timing simulation delay and number of slices were used as performance metrics. The results obtained are compared with the existing results achieved for FIR filter, thus our work proves that the objective of high speed has been achieved successfully with the use of minimum number of slices.

Highlights

The Finite Impulse Response (FIR) digital filters are widely used in digital signal processing applications due to their stability and linear phase properties
Digital Signal Processing (DSP) is widely used inreal time applications such as video, image processing and wireless communication.Multipliers and adders are the keycomponents of such high performance system such as FIR filter
We selected Galois Field multiplier for the implementation as it does not give partial product so it helps to increase the speed of the filter

Summary

Introduction

The Finite Impulse Response (FIR) digital filters are widely used in digital signal processing applications due to their stability and linear phase properties. Digital Signal Processing (DSP) is widely used inreal time applications such as video, image processing and wireless communication.Multipliers and adders are the keycomponents of such high performance system such as FIR filter. Optimizing the speed and the area of the adder and multiplier is the major task. Many previous efforts [8]-[10] have been focused on high speed, area optimization and power reduction implementations. One approach byPramod Kumar Meher et al [10] in July 2008 has proposed the design optimization of one-and twodimensional fully pipelined computing structures for area-delay-power-efficient-speed implementation of FIR filter by systolic decomposition of distributed arithmetic (DA) based inner product computation. The major difficulty encountered in this scheme is that as the filter size or the number of bits used to represent coefficients increases the memory requirement increases exponentially

Methods

Results

Conclusion