A 24–28-GHz Four-Element Phased-Array Transceiver Front End With 21.1%/16.6% Transmitter Peak/OP1dB PAE and Subdegree Phase Resolution Supporting 2.4 Gb/s in 256-QAM for 5-G Communications

Wei Zhu,Xiaohan Zhang,Jiawen Wang,Yanping Zhu,Yan Wang,Bingbing Liao,Wei Lv

doi:10.1109/tmtt.2021.3071600

Abstract

This article presents a power efficient 24-28-GHz four-element phased-array transceiver (TRX) front end (FE) for 5-G base stations and user equipment communications. A power efficient hybrid quadrature vector interpolation-based phase-shifting architecture is proposed to increase the TX and RX power efficiency and phase resolution. A transformer-based embedded T/R switch is proposed which minimizes TX and RX losses to ensure high TX output power and power efficiency while maintaining a low noise figure (NF) and extremely compact chip area. The 24-28-GHz four-element TRX FE is implemented in a 65-nm CMOS process (1P9M) for large-scale phased-array applications. The TX and RX paths achieve 0.8° phase resolution with <; 0.47°/0.17-dB RMS phase/gain error as well as 24-dB gain control range with 0.75-dB gain step and <; 0.1°/0.4-dB RMS gain/phase error over 24-30 GHz. The full TX path (including splitter and T/R switch) also achieves a measured 16.6-/18.9-dBm OP1dB/ P sat with 21.1%/16.6% PAE peak /OP1dB for each FE element while maintaining a minimum 4.4-dB NF in the full RX path (including combiner, T/R switch, and OFF-mode PA) at 28 GHz. Under the 64-/256-QAM modulation measurements, the full TX path achieves a state-of-the-art average output power of 13.5-/10.2-dBm per element (8.4%/3.5% full TX path PAE) with -26.4/-30.8 dB EVM and 27.8-/30.1-dB ACLR at 28 GHz, making the proposed TRX FE can be effectively deployed in both base stations and user equipment for 5-G communications. The chip size of the four-element TRX FE excluding I/O pads is only 3.4×1.1 mm 2 .

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