Abstract
For the hard guessing random additive noise decoding Markov order (GRAND-MO) algorithm, it is crucial to develop an efficient noise error patterns (NEPs) generator to facilitate its application in bursty channels. This paper proposes a practical hardware realization by generating the NEPs in a sequential manner. Based on classification of the four types of NEPs, we propose to iteratively calculate the “1" and the “0" permutations in the same time. Then, the novel “0" permutation regularization and bit flipping techniques are employed, through which the generation of the four types of NEPs is uniformed at the same way. Moreover, the proposed NEPs generator can generate all NEPs by using the “1" burst parameters, and is suitable for the guessing decoding of any linear block codes. Built on field programmable gate array (FPGA) implementation and comparison with existing benchmark, we show the proposed NEPs generator is a power-efficient architecture for realization. This work presents a new solution for the hardware implementation of the NEPs generator in GRAND-MO.
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