Power Distribution Network Design Research Articles

A CAD approach for pre-layout optimal PDN design and its post-layout verification

Design of power distribution network (PDN) draws great attention to integrated circuit (IC) designers as it directly affects the circuit performance. The challenge is to immune the circuit from the noise arising due to PDN by means of effective placement of decoupling capacitance (decap) with optimal power, delay, energy and area utilization. Our work involves extraction of circuit parameters in the pre-layout stage and estimating decoupling capacitance as an early prediction activity based on dynamic power dissipation. We propose a new modular pre-layout PDN (MPLPDN) design approach, which modularizes the circuit and involves a computer aided design (CAD) methodology to investigate the changes in noise, power and delay parameter based on predictive decap allocation across the modules. A pruning methodology has been adopted to choose the best combination of the modules. The modularization algorithm is applied in a bottom up approach i.e. the lower level modules are combined at first and the top level module is created at the last stage. The experimental results based on pre and post layout simulation of application circuits show that MPLPDN achieves a considerable PDN noise suppression with a negligible increase in power, delay, energy and area. The comparison between pre-layout and post-layout simulation results also establishes the correctness of our early prediction.

PCB PDN Prelayout Library for Top-Layer Inductance and the Equivalent Model for Decoupling Capacitors

The power distribution network (PDN) of a high-speed printed circuit board requires a high-performance power supply. The total equivalent inductance above the top ground plane is an important part of PDN design and is regarded as L above. In this paper, an inductance library for different structures of capacitor connections and capacitor sizes has been built, which is essential for PDN design. computer simulation technology (CST) and partial element equivalent circuit method are applied to obtain the shorted pattern design curves at various design data. The shorted pattern design curve means the total equivalent inductance varies with the distance between pad and ground plane. In addition, an approximate shorted model is established for a decoupling capacitor-mounted model, which will be convenient for us to get the inductance of L above. In this paper, the design curve provides an intuitive guideline in designing PDN and facilitates the industry to choose what they want with consideration of the inductance, space, via numbers, etc.

Z-Directed Component (ZDC) Technology for Power Integrity Applications

An important aspect of ensuring the power integrity of a power distribution network (PDN) design is to determine the layout, value, package size, and number of decoupling capacitors. To solve the limitation of the vertical connection of the surface-mounting-type capacitor to the power net area fill, a new concept of a capacitor denoted the Z-directed component (ZDC) is proposed in this paper. There are many applications possible with the ZDC with the first implementation as a decoupling capacitor. The ZDC capacitors can be integrated within the printed circuit board (PCB) substrate directly below the package ball and eliminate the integrated circuit (IC) to decoupling capacitor horizontal distance across the power net area fill. Furthermore, the inductance associated with the vertical current paths on the vias from the IC package to the horizontal power net area fill and similarly for the surface-mounted technology decoupling capacitors is eliminated. Since only the inductance of the ZDC capacitor itself remains, there is the possibility of using far fewer capacitors to achieve a high-frequency target impedance specification. The ZDC is a promising technology that gives the PCB designer the opportunity to integrate low equivalent series inductance decoupling capacitors much closer to the noise source than traditional surface-mount capacitors. In addition, in this paper, a high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements.

Parallel Plate Impedance and Equivalent Inductance Extraction Considering Proximity Effect by a Modal Approach

A modal approach for parallel plate impedance and equivalent inductance extraction for power integrity analysis including ball grid arrays (BGAs) between two parallel plates is presented. Since the BGAs are placed close to each other, the current flowing through each ball is not uniformly distributed due to the proximity effect. In this paper, a modal-based cavity method is proposed to count for this proximity effect. Analytical solutions for both the parallel plate impedance and the equivalent inductances associated with the BGAs are derived from the modal-based cavity method. The proposed method is validated by finite element method simulations and the application of the proposed method for power distribution network design is demonstrated.

Reverse Power Delivery Network for Wireless Power Transfer

RF wireless power transfer and energy harvesting have gained a lot of interest nowadays due to its importance as a convenient feature in hand-held and Internet of Things devices. One bottleneck in both these applications is on converting the received RF energy to a regulated voltage level that a mixed signal load can use. A high-efficiency switching dc–dc converter, which switches at a much lower frequency than the RF frequency, is required for this purpose. This poses a unique design challenge in connecting these two very different frequency domains. This letter proposes an innovative solution for this problem, by demonstrating a new design method called a reverse power distribution network (PDN), a concept originating from the conventional processor PDN design. Experimental results are provided to support the proposed design approach.

Inductance Extraction of Grid Power Distribution Network

For the package or on-chip power distribution network (PDN) design, plane metals are usually adopted. In this paper, we propose a closed-form grid metals solution to calculate the inductance of such grid PDN for the frequencies below its first antiresonant frequency. First, the grid PDN is equivalent to a plane PDN based on the equivalent circuit of their unit cells. Furthermore, the equivalent plane PDN is simplified as an RLCG lumped circuit, where ${L}$ is the inductance of the grid PDN. Finally, the inductance of the grid PDN is obtained by the mode analysis of the equivalent plane PDN with a modified modal function. The proposed method is scalable, which can calculate the grid PDNs with the size from micrometer to centimeter. To verify the proposed method, a centimeter grid PDN is fabricated. The inductance obtained by the proposed method has a good agreement with that obtained by measurement and 3-D full-wave simulation. The proposed method can also be expanded to the case that the grid PDN has load impedances. In comparison with the numerical methods, the proposed method can give a more easy-to-understand explanation of the new antiresonant frequency produced by the load impedance.

SMT-Based Observer Design for Cyber-Physical Systems under Sensor Attacks

We introduce a scalable observer architecture, which can efficiently estimate the states of a discrete-time linear-time-invariant system whose sensors are manipulated by an attacker, and is robust to measurement noise. Given an upper bound on the number of attacked sensors, we build on previous results on necessary and sufficient conditions for state estimation, and propose a novel Multi-Modal Luenberger (MML) observer based on efficient Satisfiability Modulo Theory (SMT) solving. We present two techniques to reduce the complexity of the estimation problem. As a first strategy, instead of a bank of distinct observers, we use a family of filters sharing a single dynamical equation for the states, but different output equations, to generate estimates corresponding to different subsets of sensors. Such an architecture can reduce the memory usage of the observer from an exponential to a linear function of the number of sensors. We then develop an efficient SMT-based decision procedure that is able to reason about the estimates of the MML observer to detect at runtime which sets of sensors are attack-free, and use them to obtain a correct state estimate. Finally, we discuss two optimization-based algorithms that can efficiently select the observer parameters with the goal of minimizing the sensitivity of the estimates with respect to sensor noise. We provide proofs of convergence for our estimation algorithm and report simulation results to compare its runtime performance with alternative techniques. We show that our algorithm scales well for large systems (including up to 5,000 sensors) for which many previously proposed algorithms are not implementable due to excessive memory and time requirements. Finally, we illustrate the effectiveness of our approach, both in terms of resiliency to attacks and robustness to noise, on the design of large-scale power distribution networks.

Sensitivity Analysis of a Circuit Model for Power Distribution Network in a Multilayered Printed Circuit Board

Power distribution network (PDN) design in high speed digital systems is a critical challenge for system performance. Common design methodologies refer to guidelines and engineering best practices while using simulations to evaluate the design. If the relation between the design choices and the performance parameters is known, the engineering is simpler. A lumped circuit model that relates physics and design geometry was proposed in an earlier study for modeling practical printed circuit board (PCB) PDN designs. In this paper, the lumped circuit model proposed earlier is used to develop a well-defined relation between the design geometry, the model elements, and the PDN impedance response features. The PDN impedance is simplified and broken down into common features for all PCB PDNs. These features are mapped to the model elements using sensitivity analysis and consequently to design geometry. The physics behind the relation between the response and geometry is reinforced with the current paths in different frequency ranges and generalized to common PDN designs on multilayer PCBs that use area fills for the power net.

Inductance Extraction for PCB Prelayout Power Integrity Using PMSR Method

Proper power integrity (PI) analysis is required for printed circuit board (PCB) power distribution network (PDN) design. Top-layer interconnect inductance for PI has always been a vital concern for high-speed industry. Developing a simple physics-based equivalent circuit model for critical structures is essential for understanding the physics of the system and for intelligent designs. In this paper, a physics-based model size reduction (PMSR) method is applied to get the equivalent circuit model for the above-ground geometries. The extracted physics-based models are also based on the partial element equivalent circuit (PEEC) method, and can be used in analyzing the structure in its parts. By applying PMSR method, a physics-based equivalent circuit model can be proposed and this circuit model is related to the geometric features of the design. In this way, PMSR method can provide an intuitive guideline in designing PCB and reducing above inductances, therefore, a low-ripple dc voltage can be delivered through PDN. Taking advantage of PEEC and PMSR methods, the top-layer inductances of three different geometries are calculated and the physics-based circuit models are obtained, respectively.

Quantified Design Guides for the Reduction of Radiated Emissions in Package-Level Power Distribution Networks

Closed-form expressions of radiated emissions from power distribution networks (PDNs) in packages are derived based on the equivalent lumped-circuit model. The expressions are validated with results from full-wave numerical computations and far-field measurements. The effects of the small planar PDN structures on radiated emissions are quantitatively investigated based on the sensitivity analysis. Using the closed-form expressions, a systematic procedure for developing quantified PDN design guidelines to suppress the radiated emissions is formulated, which is then demonstrated with a test prototype PDN. The method allows the electromagnetic compatibility aware PDN design in the initial design stage.

Defining priorities in the design of power and water distribution networks

This paper presents an approach for designing power and water distribution networks involving the sizing, geographic location, as well as the economic, environmental and social impacts, and taking into account the multiplicity of criteria for the stakeholders involved in the development of operational policies and new facilities. In this paper is presented a method for defining solutions concerning to the design of power and water distribution networks based on a multi-stakeholder environment. A multi-objective model, considering economic, environmental and social factors, is used for illustrating how the different criteria, about priorities of the stakeholders, affect the design of the system and how to propose a solution for achieving a tradeoff between the multiple stakeholders. The proposed method was applied to an electric and water stressed scheme in the north of Mexico, the results show that the minimization of the dissatisfaction of the involved systems can provide an optimal solution that meets the objectives of all stakeholders.

Signal integrity

Welcome to the Signal Integrity Column! In this issue, we go back to an interesting topic in Power Integrity: the dynamic behavior of the power distribution network in terms of charge delivery when an active device switches. Providing sufficient charge in a timely fashion is key for the power distribution network to achieve high-speed logic-state transitions for functionality requirements. Thus, understanding the dynamic behavior is essential to understand the physics and ensure a successful power distribution network design for high-speed circuits. Even though the topic has been well studied, the author presents a clear and comprehensive review with practical examples in this paper. I am sure the EMC Magazine readers will find this paper interesting and enlightening to read.

Effect of magnetic coupling between the mounting loops of two parallel capacitors on antiresonance

A microprocessor board comprises many capacitors in parallel for decoupling purposes. Due to space constraints, they are kept close to each other. When two capacitors with different self-resonant frequencies are connected in parallel, between their self-resonant frequencies an impedance peak known as antiresonance is introduced. If the capacitors are placed close to each other, their mounting loops are magnetically coupled. This coupling affects the antiresonance peak value, which is studied in this study. An expression for the peak value of antiresonance is derived using circuit theory, and it is compared with accurate solutions obtained in Matlab™. A general critical damping condition is formulated based on this. The expressions are validated with simulation and experimental studies. The obtained results will be useful for improving capacitor selection algorithms used in power distribution network design by incorporating the coupling effects into the constraints.

Concurrent optimisation method for three‐dimensional power delivery network design

Power distribution network (PDN) design in three-dimensional integrated circuit (3D IC) is one of the most important challenges. Power wires and power bumps or power through-silicon-vias (TSVs) are the two major factors that affect the voltage as the IR-drop of 3D ICs. Different parameters of power wires and different insertions of power bumps/TSVs cause different IR-drop distribution. In this study, the authors propose 3D power concurrent optimisation to achieve a multi-objective design for 3D IC PDN, which optimises the insertion of power bumps/TSVs according to the IR-drop distribution and concurrently reduces the power wire's routing area so as to lower the metal coverage rate, guaranteeing the IR-drop and other constraints. Results of the experiments show that the proposed method can get more solutions than one after a run with both less power routing area and less number of power bumps/TSVs. In addition, the experiments also show that it is more effective and efficient than the classical exhaustive method.

Challenges and solutions for core power distribution network designs

Core power decoupling for modern processors or SOCs is a challenging task due to large power consumption. A conventional target impedance method can no longer be used in modern high-performance core PDN design. In this paper, we first demonstrate major issues and challenges in existing PDN modeling methodologies. Then, we present a comprehensive list of PDN improvements which significantly eliminates pessimism built in existing methods. In particular, we propose an improve VRM model to reduce the PCB bulk cap requirements, an accurate PCB decoupling frequency range to reduce the PCB SMC cap, a modified target impedance concept to account for realistic ramp time for large load change, and a novel timingbased PDN design methodology to further reduce any pessimism in traditional noise based PDN design methodology.

Multi‐objective design of advanced power distribution networks using restricted‐population‐based multi‐objective seeker‐optimisation‐algorithm and fuzzy‐operator

This study proposes a method for designing advanced power distribution system (PDS) including distributed generations, using a combination of fundamental loop generator and multi-objective seeker-optimisation algorithm (MOSOA). The proposed approach reduces the searching space using fundamental loop generator technique to obtain initial feasible solutions which is further improved by SOA to generate new set of solutions with improved aptitude. The proposed methodology uses a contingency-load-loss-index for reliability evaluation, which is independent of the estimation of failure rate and fault repair duration of feeder branches. This planning strategy includes distribution automation devices such as automatic reclosers (RAs) to enhance the reliability of PDS. The proposed algorithm generates a set of non-dominated solution by simultaneous optimisation of two conflicting objectives (economic cost and system reliability) using Pareto-optimality-based trade-off analysis including a fuzzy-operation to automatically select the most suitable solution over the Pareto-front. The performance of the proposed approach is assessed and illustrated on 54-bus and 100-bus PDS, considering realtime design practices. Extensive comparisons are made against some well-known and efficient MO algorithms such as fast non-dominated sorting genetic algorithm-II, MO particle- swarm-optimisation and MO immunised-particleswarm-optimisation. Simulation results show that the proposed approach is accurate and efficient, and a potential candidate for large-scale PDS planning.

Accurate IC current extraction method and power distribution network optimization

ABSTRACTObtaining correct integrated circuit (IC) current information is a key factor for power distribution network design. This letter suggests an exact IC current extraction method using a measured voltage of a board when detailed IC data cannot be accessible. Voltage waveform is measured at the closest decoupling capacitor position from an IC after the capacitor is eliminated. Using the measured voltage and new transfer function which eliminates oscilloscope probe noise effect, we are able to calculate an exact IC current. The proposed methodology is validated by comparing the simulated noise voltage with the real measured noise voltage of 1.2 V core circuit. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2175–2182, 2015

Analysis of Impedance & Supply Noise for Power Distribution Networks in IC Using CM

With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power distribution networks poses a difficult problem in modern IC design. We propose several closed-form solutions for power distribution network optimization and analysis which explicitly take into consideration the mesh topology. An RLC model for on-chip power distribution networks is presented for array and wire bonded integrated circuits including inter block decoupling capacitors and impedances. One of the more common design techniques for power distribution networks PDN is the determination of the impedance & supply noise. Current-mode technique is used. By using this current mode technique noise and impedance, voltage is analyzed.

Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors

An $RLC$ model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any point of the circuit are calculated as a function of frequency and PDN parameters. The proposed method to perform such calculation allows optimizing relevant PDN design parameters, such as number, size, and location of supply/ground pads and location of interblock decoupling capacitors, and width and pitch of metal tracks. The PDN model and impedance calculations are validated by comparing their results with SPICE simulations, giving a maximum error of less than 1%.

Diagnosis and optimization of a power distribution network by extracting its parasitic inductances and building a lumped circuit model

Design of power distribution networks (PDNs) in high speed digital circuit has become a more challenging task in view of decreasing supply voltages and increasing transient currents. The parasitic inductance of a PDN is the most crucial parameter that limits high frequency performance. In this paper, a specific PDN on printed circuit board (PCB), with multiple supply voltages, is diagnosed and optimized. A simple method is developed to extract the parasitic inductances of the PDN by examining the Y parameters. An equivalent lumped circuit model is built to interpret the input impedance curve of the PDN. Based on this model, a simpler circuit model is presented. Predictions based on the simple circuit model are in agreement with the field simulated performance of the whole structure and with measured results. The performance of the PDN can be improved by optimizing segmentation and distribution of power planes along with strategic placement of decoupling capacitors. It is crucial for PDN design to decrease the parasitic inductance between power/ground pads on PCB and their junction points to PDN power/ground pairs.