Abstract
Power distribution network (PDN) design in three-dimensional integrated circuit (3D IC) is one of the most important challenges. Power wires and power bumps or power through-silicon-vias (TSVs) are the two major factors that affect the voltage as the IR-drop of 3D ICs. Different parameters of power wires and different insertions of power bumps/TSVs cause different IR-drop distribution. In this study, the authors propose 3D power concurrent optimisation to achieve a multi-objective design for 3D IC PDN, which optimises the insertion of power bumps/TSVs according to the IR-drop distribution and concurrently reduces the power wire's routing area so as to lower the metal coverage rate, guaranteeing the IR-drop and other constraints. Results of the experiments show that the proposed method can get more solutions than one after a run with both less power routing area and less number of power bumps/TSVs. In addition, the experiments also show that it is more effective and efficient than the classical exhaustive method.
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