Inductance Extraction for PCB Prelayout Power Integrity Using PMSR Method

Abstract

Proper power integrity (PI) analysis is required for printed circuit board (PCB) power distribution network (PDN) design. Top-layer interconnect inductance for PI has always been a vital concern for high-speed industry. Developing a simple physics-based equivalent circuit model for critical structures is essential for understanding the physics of the system and for intelligent designs. In this paper, a physics-based model size reduction (PMSR) method is applied to get the equivalent circuit model for the above-ground geometries. The extracted physics-based models are also based on the partial element equivalent circuit (PEEC) method, and can be used in analyzing the structure in its parts. By applying PMSR method, a physics-based equivalent circuit model can be proposed and this circuit model is related to the geometric features of the design. In this way, PMSR method can provide an intuitive guideline in designing PCB and reducing above inductances, therefore, a low-ripple dc voltage can be delivered through PDN. Taking advantage of PEEC and PMSR methods, the top-layer inductances of three different geometries are calculated and the physics-based circuit models are obtained, respectively.