Switching Energy Research Articles

Design of Low Power SAR ADC with Novel Regenerative Comparator

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).

High Performance and Scalable Hybrid Memristor-CMOS Based Full Adder

The field of digital computation has recently drawn attention to the memristor as a circuit element due to its nanoscale structure and integration capabilities with MOSFETs. As a result, there have been various attempts to use hybrid memristor-CMOS circuits to rebuild the fundamental digital building blocks. This paper presents a new hybrid memristor-CMOS-based full adder (HMC-FA) design. This design aims to minimize propagation delay, power dissipation, power delay product (PDP), and device count (memristor and transistor count). The proposed design is implemented in Cadence Virtuoso toolset utilizing CMOS gpdk 180nm process technology parameters. Comparative investigation demonstrates that the proposed HMC-FA improves PDP by 71.95%−99.83%. The proposed circuit is designed with 12 transistors and 6 memristors. The proposed design consumes 8.24µW of total power while the propagation delay is 112.71ps at 1.8V supply voltage. To verify the scalability of the HMC-FA cell, full adders up to 32-bit word length are designed, and performance parameters are evaluated at 1.8V, 100MHz supply voltage.

Potensi Pemanfaatan Biogas Dari Sampah Organik Sebagai Sumber Energi Terbarukan

Waste is one of the most serious problems experienced by the world, and Indonesia is no exception. Waste generated by human activity or nature will continue to increase, if this waste is not managed properly, it will cause new problems such as being a source of disease, can cause global warming and can cause foul odors. On the other hand, energy demand will continue to increase along with the increasing population and economic growth. The limitations of available energy sources are dwindling, thus demanding attention to switch energy sources using renewable energy sources to meet the increasing energy needs. This study aims to identify the potential utilization of biogas from organic waste in various potential applications that can support renewable energy sources. In this research, the method used is a literature study which is analyzed by descriptive analysis method. The results obtained in this study are the making of biogas is done by several processes and using a digester. This biogas has the potential to be a renewable energy source because it contains very high methane and carbon dioxide compounds. Biogas from organic materials can be used as cooking fuel, a substitute for petrol (gasoline), lighting, and power generation. Of course, the utilization of biogas from organic waste can reduce the amount of waste supply and become a source of energy that is very beneficial for daily life.

A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications.

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

Implementation of Taguchi Method in Improving the Logic Gates Performance based on Carbon Nanotube Field Effect Transistor Technology

The International Roadmap for Device and Systems (IRDS) 2022 has emphasized the potential of CNTFETs to replace CMOS technology. Therefore, the substitution of silicon with carbon nanotubes (CNTs) has the potential to open new possibilities for the semiconductor industry, due to their compact size and superior electrical properties. Thus, this project utilized Cadence Virtuoso software to develop an optimized CNTFET design using Taguchi method. In this design, the Taguchi method was implemented to determine the best combination of design parameter and material for optimum CNTFET performance. The design parameter and material that had been chosen were the diameter of carbon nanotube, dielectric material and oxide thickness. The optimized CNTFET model is implemented in circuit study to analyse the propagation delay and power consumption. Five circuits had been designed from the optimized CNTFET which are the inverter, AND, OR, NAND and NOR circuit. The Taguchi Optimization method resulted in significant reductions in the power- delay product (PDP) for all circuits examined, ranging from 7.9954% for the AND circuit to an exceptional 99.9622% for the inverter circuit. These findings highlight the potential for improved power efficiency and faster circuit operation when utilizing the Taguchi Optimization approach.

POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP

Flip-flops are the fundamental building blocks of the data path structure. It is a key component of digital circuits and systems. This work offers an exclusive master-slave flip-flop topology by ensuing clocked complementary metal oxide semiconductor (C2MOS) logic, minimizing the total device count and the count of clocked devices. Reducing the number of clocked devices reduces undesirable transient activity and reduces dynamic power dissipation. C2MOS logic connects static logic design with clock signal synchronization, resulting in power savings and increased speed. The area reduction is also attained by reducing the total number of devices. The proposed topology has been realized using only sixteen transistors, including six clocked devices, resulting in area compression. Layout-level simulation at 0.12 mm C2MOS design rule technology is used to investigate the performance. According to an investigation, the proposed topology achieves power savings ranging from 19.77 to 63.75 %, area compaction ranging from 22.03 to 66.30 %, power delay product (PDP) enhancement ranging from 18.56 to 53.91 %, energy-delay product (EDP) enhancement ranging from 5.61 % to 41.39 %, power energy product (PEP) enrichment ranging from 35.63 to 82.82 %, and power area product (PAP) enrichment ranging from 35.19 to 66.30 %.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

4:2 Compressor Design for Low Leakage Applications in FinFET Technology

The increased short-channel effects in the ultra-nanoscale regime limit the operation of complementary metal oxide semiconductor (CMOS) technology. To combat the issues in the ultra-nanoscale regime, fin-shaped field effect transistor (FinFET) technology is the best choice because of its numerous advantages over CMOS technology. FinFET enhances the further scaling of the devices and control over the channel. Therefore, this research paper presents the implementation of a low leakage 4:2 compressor in FinFET technology. A compressor is a general block, especially used in multiplier units and hence in digital signal processing (DSP) systems. The design of the low power compressor improves the overall efficiency of the DSP systems. An extensive study of the proposed low power 4:2 compressor at 7 nm technology node is done in the paper. Mentor Graphics tools are used for the circuit simulations and analyzes. The key parameters, such as leakage power, delay, power delay product (PDP), and the process voltage temperature (PVT) variations, are estimated for the performance evaluation. The proposed 4:2 compressor saves 87.33% of leakage power and is 75.90% more energy efficient compared to its conventional counterpart.

A review of crosstalk polymorphic circuits and their scalability

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.

A 10-bit 33.3-kS/s 3.2-fJ/conversion-step single-ended counter-type SAR ADC with dual 5-bit CDAC arrays and counters in 65-nm CMOS

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM.

A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

Ternary encoder and decoder designs in RRAM and CNTFET technologies

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

Ultra-low reverse leakage in large area kilo-volt class β-Ga2O3 trench Schottky barrier diode with high-k dielectric RESURF

We introduce vertical Schottky barrier diodes (SBDs) based on β-Ga2O3 with trench architecture, featuring a high-permittivity dielectric RESURF structure. These diodes are designed for application demanding high voltage and current capacities while maintaining ultra-low reverse leakage currents. The trench design plays a pivotal role in reducing the electric field at the metal–semiconductor junction, thereby yielding minimal reverse leakage attributed to field emission under high reverse bias conditions. Additionally, the incorporation of a high-k dielectric helps to suppress leakage through the trench bottom corner dielectric layer. The small area trench SBD (200 × 200 μm2) demonstrates a breakdown voltage exceeding 3 kV, accompanied by a reverse leakage current of less than 1 μA/cm2 at 3 kV. Moving on to larger area devices, the 1 × 1 and 2 × 2 mm2 devices exhibit breakdown voltages of 1.8 and 1.4 kV, while accommodating pulsed forward currents of 3.5 and 15 A, respectively. The capacitance, stored charge, and switching energy of the trench SBDs are also found to be less than the similarly rated commercial SiC SBDs, reinforcing their potential for enhanced switching efficiency.

A DFT study on the switching energy of multiferroic capacitor with stable single-phase multiferroic material

In spintronic technology, bismuth ferrite BiFeO3 (BFO) is a potential multiferroic material for multiferroic capacitor application. In present study, the impact of transition metals X = Co, Ni, Mn, Ti at the Fe-site and rare earth element lanthanum (La) at the Bi-site is investigated using DFT calculation in order to improve the structural stability, spin polarized electronic, and dielectric properties of bismuth ferrite for switching energy of multiferroic capacitor applications. The calculations are carried out in the Cambridge Serial Total Energy Package (CASTEP) code by using ultra-soft pseudopotential (USP). The substitution of La and X atoms alters the spin-polarizedelectronic and dielectric characteristics of BFO, leading to an increase in the density of states (DOS) around the Fermi level. The observed descending order of the structure stability of co-doped BFO is given as: LaCo > LaNi > LaMn co-doped BFO system. LaCo and LaNi co-substituted systems have shown high spin polarizations of 87.08 % and 82.20 % respectively. Low switching energies of 0.52 aJ and 0.72 aJ, respectively have been observed for LaCo and LaNi co-doped BFO systems for multiferroic RAM capacitor applications.

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

AbstractStatic random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

Design of soft error correction flip-flop cells for highly reliable applications

With the development of technology, the vulnerability of integrated circuits to Single Event Effect (SEE) increases, and the sensitivity of flip-flops to soft errors induced by Single Event Transient (SET) and Single Event Upset (SEU) increases. Fault tolerant design is necessary for high reliability applications. In this work, a Soft Error Correction Flip-Flop 1(SEC FF1) is proposed, which can correct soft errors induced by SET and SEU at low clock phase without additional clock cycle. It has the lowest area and power consumption overhead and the lowest Power-Delay Product (PDP) compared with other radiation hardened flip-flops. In order to correct soft errors earlier, a variant of SEC FF1, SECFF2, is proposed at the cost of power consumption and switching delay. As the feature size of transistors shrinks, Double Node Upset (DNU) induced by single-event charge sharing is becoming an emerging reliability challenge. In order tolerate DNU, variant of SEC FFs, DNU Correction (DNUC) FFs, are proposed. In addition, the delay element used in the radiation-hardened flip-flops is also introduced.

Novel Architecture of Fir Lattice Filter with Reduced Interconnect Delay Impacts Towards Reduced Power-delay Product using Pipelining and Parallel Processing for Medical Applications

Three important parameters area, speed and power are important. In VLSI design, the speed is determined by the critical path delay. Delay is depending on the data path taken for processing in the VLSI design. By minimizing data-path delay using efficient architecture the speed of the design of system can be improved in turn to result in better performance. In this new era, data-path delay is the dominating one compared to logic delay. So, it is very essential to concentrate more towards path delay in any architecture design. Even though the speed is important it is having in trade of with power. This data-path delay can be reduced by different technique like pipelining, parallel processing, register retiming. Also, by constructing this architecture in an innovative way the power is having trade of with delay. So the power-delay product can be taken as the reduced one. In this paper, various architecture of delay-product optimized FIR filter and Lattice filter architecture is being surveyed and implemented in order to get minimum delay-power product

Modeling and performance analysis of F-functionalized AGNR reconfigurable logic gates

The paper investigated F-functionalized armchair graphene nanoribbons using the density functional theory. The band structures and densities of states of all AGNR configurations demonstrate the semiconducting nature and can be tuned by taking F-passivation at different edges. Based on binding energy calculations, F@edge_100% AGNR found the most stable configuration compared with other AGNRs. F@edge_100% AGNR device is proposed for nanoscale reconfigurable logic gates. Further comprehensive analysis is done for performance parameters i.e. quantum propagation delay (τp), switching energy (Esw), power dissipation (Pd) of the proposed device. F@edge_100% AGNR confirms the less device area, low propagation delay and lower switching energy. Further in F@edge_100% AGNR device, speed is high and power consumption becomes low as compared to CMOS technology. The proposed device shows the potential for futuristic nanoscale low power and high speed reconfigurable digital logic gates.

A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit

In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices, a bridged-switch energy-efficient switching scheme for successive approximation register (SAR) ADCs with a low-complexity capacitor drive circuit is proposed. The technique of top-plate sampling and closed-loop charge recycling is used in the proposed switching scheme so that neither the first nor the second comparison consumes switching energy. The third comparison uses bridge switches to connect the subarray to the main array, effectively reducing switching’s energy consumption. Only the least significant bit (LSB) is dependent on the accuracy of Vcm; thus, the last comparison consumes little switching energy. The proposed switching scheme achieves an average switching energy value of 47.5 CV2ref, which is 96.52% lower than that of the conventional capacitor switching scheme and reduces the area by 75%. The other major circuit modules employed are bootstrapped switches, a fully dynamic comparator, and dynamic SAR logic. The proposed ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in a 9.8-bit effective number of bits (ENOB), a signal-to-noise and distortion ratio (SNDR) of 60.76 dB, a spurious-free dynamic range (SFDR) of 69.85 dB, a power consumption of 14.7 μW, and a figure of merit (FoM) of 16.55 fJ/conv.-step.

Design and Performance Analysis of Logic Circuits using FinFET Technology

As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. To reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETs like FinFET (Fin Field Effect Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers and designers. FinFET is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFET technology. This document is a review paper of current research on FinFET technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFET like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFET technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range.