Circuit Power Consumption Research Articles

Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology

This work analyzes a set of Full Adder circuits considering variability effects, comparing delay and energy consumption when operating at nominal voltage and near-threshold voltage. The decoupling cell technique was adopted for reducing process variability effects. It is evaluated traditional adders and XOR-based adders in different scenarios, from traditional nominal conditions to circuits with decoupling cells addition. Mirror Adder still is the best alternative to performance optimization at nominal voltage operation. The near-threshold operation can reduce the power by 97% on average for the evaluated circuits, with penalties of 6.4 times on delay and increasing up to 2 times the process variability sensitivity. XOR-based FAs are less sensitive to process variability effects on power, independently of the voltage operation. Moreover, the decoupling cell technique brought benefits to all evaluated adders about the mitigation of process variability effects on power, since this technique introduces a reduction in the power consumption of the circuits. So, the use of decoupling cells demonstrates to be a good option to achieve greater robustness to variability impact regarding the circuits power consumption. • Process Variability affects the expected behavior of circuits at nanometer nodes. • FinFET devices show better control of short-channel effects and radiation robustness. • Even so, process variability is a considerable challenge. arithmetic blocks. • This work proposes adoption of XOR-based Full Adders, together with the decoupling cells mitigation technique, to reduce the process variability deviation. • Decoupling cells brought benefits to all evaluated adders about the mitigation of process variability effects on power.

Artificial Intelligence for Physical-Layer Design of MIMO Communications with One-Bit ADCs

Wireless systems continue to go toward higher carrier frequencies, including terahertz bands, to take advantage of higher bandwidth channels. At the same time, antenna arrays remain important with continued increases in array elements. However, the power consumption of RF and digital circuits can increase proportionally to both the amount of signal bandwidth and the number of antennas. The use of one-bit analog-to-digital converters at the receiver is a cost- and power-efficient solution for wideband and/or massive antenna wireless systems. The nonlinearity of one-bit received signals brings challenges in physical-layer (PHY) design at the receiver. At the same time, the binary nature of these signals opens new opportunities for artificial intelligence (AI)-based PHY design. This article covers recent progress in incorporating AI into the design of classical PHY techniques and emerging studies on establishing AI-inspired frameworks that fundamentally replace classical model-driven techniques with data-driven AI techniques. It concludes with a discussion, including practical challenges and future research directions.

A novel voltage protection method for multi-cell lithium-ion battery protection IC

Lithium batteries have been widely used in portable electronic devices and other electric products. To ensure safety and long life, a lithium battery needs to be equipped with a protection chip. A novel voltage protection method for three-cell lithium-ion battery protection IC (Integrated Circuit) is proposed in this paper. A new voltage protection circuit structure and a three-cell lithium battery voltage sampling circuit are presented to improve the circuit performance of the chip and reduce the dynamic power consumption and chip area of the system. With a new time-division multiplexing circuit structure, the area and power consumption of the chip are greatly reduced. Moreover, this solution can be extended to any number of lithium battery packs connected in series for voltage protection. Testing results show that the overcharge detection accuracy can achieve better than ±15mV, the over-discharge detection accuracy can achieve ±7.5mV, the power consumption of the voltage protection module is 1.7μA, and the area is 300μm×500μm2.

Rate-Splitting Multiple Access for Multi-Antenna Downlink Communication Systems: Spectral and Energy Efficiency Tradeoff

Rate-splitting (RS) has recently been recognized as a promising physical-layer technique for multi-antenna broadcast channels (BC). Due to its ability to partially decode the interference and partially treat the remaining interference as noise, RS is an enabler for a powerful multiple access, namely rate-splitting multiple access (RSMA), that has been shown to achieve higher spectral efficiency (SE) and energy efficiency (EE) than both space division multiple access (SDMA) and non-orthogonal multiple access (NOMA) in a wide range of user deployments and network loads. As SE maximization and EE maximization are two conflicting objectives in the moderate and high signal-to-noise ratio (SNR) regimes, the study of the tradeoff between the two criteria is of particular interest. In this work, we address the SE-EE tradeoff by studying the joint SE and EE maximization problem of RSMA in multiple input single output (MISO) BC with rate-dependent circuit power consumption at the transmitter. To tackle the challenges coming from multiple objective functions and rate-dependent circuit power consumption, we first propose two models to transform the original problem into two single-objective problems, namely, weighted-sum method and weighted-power method. A low-complexity algorithm with closed-form solution is proposed to solve each single-objective problem in the two-user system. For the generalized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -user system, a successive convex approximation (SCA)-based algorithm is then proposed to optimize the precoders of each transformed problem. Numerical results show that our algorithm converges much faster than existing algorithms. In addition, the performance of RSMA is superior to or equal to SDMA and NOMA in terms of SE, EE and their tradeoff.

Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

Energy Efficiency of Full- and Half-Duplex Decode-and-Forward Relay Channels

This article studies the energy efficiency (EE) of a three-node decode-and-forward (DF) relay channel, where the relay operates in full-duplex (FD) or half-duplex (HD) mode. In particular, for the FD mode, both the residual self-interference (RSI) and the extra circuit power consumption introduced by the self-interference cancellation (SIC) at the relay node are considered and modeled as linear functions over the relay transmission power. Under this setup, the EE maximization problems for the considered FD and HD modes subject to the total transmission power and spectral efficiency (SE) constraints are formulated as max–min problems, whose optimal power allocation is computed by fractional programming. Next, the EEs for the FD, HD, and direct transmission (DT) modes are compared under different channel conditions, and a hybrid mode selection scheme, i.e., selecting the one with the maximum EE among the above three modes, is proposed. Besides, we also prove that both the EE and the SE monotonically increase with the total transmission power under a given condition. Finally, numerical results show that the maximum EE of the FD relaying exceeds those of the HD and DT ones when the required SE is relatively high. Furthermore, the proposed hybrid mode selection scheme can provide up to 192.4% higher EE compared with the DT mode.

Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction

Ever-growing edge applications often require short processing latency and high energy efficiency to meet strict timing and power budget. In this work, we propose that the compact long short-term memory (LSTM) model can approximate conventional acausal algorithms with reduced latency and improved efficiency for real-time causal prediction, especially for the neural signal processing in closed-loop feedback applications. We design an LSTM inference accelerator by taking advantage of the fine-grained parallelism and pipelined feedforward and recurrent updates. We also propose a bit-sparse quantization method that can reduce the circuit area and power consumption by replacing the multipliers with the bit-shift operators. We explore different combinations of pruning and quantization methods for energy-efficient LSTM inference on datasets collected from the electroencephalogram (EEG) and calcium image processing applications. Evaluation results show that our proposed LSTM inference accelerator can achieve 1.19 GOPS/mW energy efficiency. The LSTM accelerator with 2-sbit/16-bit sparse quantization and 60% sparsity can reduce the circuit area and power consumption by 54.1% and 56.3%, respectively, compared with a 16-bit baseline implementation.

Breaking the Speed-Power Tradeoffs in Broadband Circuits: Reviewing design techniques for transceivers up to 56 GHz

The power consumption of broadband circuits used in wireline systems becomes increasingly more critical as higher speeds are sought. This article presents a number of design techniques that greatly relax the tradeoffs between the speed and power consumption of functions such as multiplexers (MUXs), frequency dividers, and equalizers. Examples include quadrature multiplexing, charge steering, and feedforward techniques. The concepts have been demonstrated in CMOS transceivers up to 56 GHz.

Comparative Analysis of Optimization Schemes of Carry Look-ahead Adder

Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder structure can be improved by designing the carry term Field Effect Transistor (FET) network and replacing the existing gate circuit with a hybrid Gate diffusion technology (GDI) gate, which can reduce the number of transistors and the design circuit area. They also contribute to improving the power consumption, delay, power delay product (PDP) and other performance parameters. Pipeline technology and multi-layer CLA block technology are suitable for carry look-ahead adder with more bits and longer carry chain, which can shorten carry propagation time, further optimize processor performance and improve CPU computing efficiency.

5‐3: A Random Access Gate Driver Using a‐IGZO TFTs for External Compensation of High‐Resolution, High‐Frame‐Rate AMOLEDs

The external compensation of AMOLED pixels that is regarded as essential for large‐area displays needs a random access gate driver to select any gate line in vertical blank time. Also, for high‐resolution, high‐frame‐rate, and large‐area displays, a gate driver with overlap driving is needed for high pixel charging ratio. In this study, a decoder‐based random access gate driver with overlap driving is proposed and verified by HSPICE simulation and fabrication of the circuits with a‐IGZO TFTs. The proposed decoder composed of TFTs in parallel enables the random access and overlap driving without increase in circuit area and power consumption.

Adaptive droop control of unbalanced voltage in the multi-node bipolar DC microgrid based on fuzzy control

• The new voltage unbalance coefficient and voltage deviation index of multi-node bipolar DC microgrid are defined to obtain more accurate parameters to describe the degree of voltage imbalance. • The influence of neutral resistance and unbalanced load on droop control is discussed. • The voltage deviation, voltage unbalance coefficient, and SOC are adopted as inputs to adjust the voltage droop coefficient in the fuzzy controller. Multi-node bipolar DC microgrid can provide more voltage level interfaces and has higher security and reliability than the unipolar DC microgrid. However, in the multi-node bipolar DC microgrid, the operation of load and line resistance will lead to the deviation of DC bus voltage and increase the circuit power consumption which will affect the stable operation of the whole microgrid. In order to control the unbalanced voltage, an adaptive droop controller based on the fuzzy algorithm is innovatively applied in the design of a multi-node bipolar DC microgrid. This research mainly analyzes the influence of unbalanced load and line resistance on droop control in the multi-node bipolar DC microgrid. According to the analysis, an adaptive droop controller based on the fuzzy algorithm with the voltage deviation, voltage unbalance coefficient, and state of charge (SOC) as inputs is designed to obtain the correction of the droop coefficient. The model of a multi-node bipolar DC microgrid is established in MATLAB/Simulink platform and the effectiveness of the proposed adaptive droop control based on the fuzzy algorithm is verified through the simulation results.

Low-noise delta-sigma analog front end with capacitor swapping technique for capacitive microsensors

In this paper, low-noise incremental delta–sigma analog front end (AFE) integrated circuit (IC) for capacitive microsensors is presented. A conventional capacitance-to-digital converter (CDC) mainly uses a multi-stage capacitive sensing amplified stage (CSA) and analog-to-digital converters. The multi-stage CSA is not suitable for application in various Internet of things (IoT) devices that require low power because the power consumption of the analog front-end circuit increases in proportion to the number of amplifiers and the chip area increases. So, the presented delta-sigma AFE can convert the capacitance changes to the digital codes directly. This structure can achieve a small active area and low power consumption. The delta–sigma AFE achieves low-noise and high linearity using a capacitor polarity swapping technique. The measured effective resolution is 16.2 bits, and the non-linearity is 0.05% full-scale output (FSO). The integrated circuit is implemented in a 0.18-µm standard CMOS process. All functional blocks, including the analog circuits (bandgap reference, voltage reference, and delta–sigma capacitance-to-digital converter) and digital block (accumulator and timing generator), are integrated on a chip. The proposed incremental delta–sigma AFE consumes 1.12 mW of power from a 3.3-V supply at a sampling frequency of 500 kHz and occupies a total active area of 0.42 mm2.

Resource Allocation for Intelligent Reflecting Surface Assisted Wireless Powered IoT Systems With Power Splitting

This paper proposes a new transmission policy for intelligent reflecting surface (IRS) empowered wireless powered internet of things systems. Particularly, an energy station (ES) wirelessly charges for multiple IoT devices during downlink wireless energy transfer (WET) and then these devices deliver their own message to an access point (AP) during uplink wireless information transfer (WIT). Also, an IRS is deployed to improve energy harvesting and data transmission capabilities. To enhance self-sustainability of the IRS, the IRS harvests energy from the ES based on the harvest-then-transmit protocol. In this paper, we maximize the sum throughput via optimizing the phase shifts of the IRS, the transfer time scheduling as well as the power splitting ratio. Due to the non-convexity of the formulated problem, we divide the problem into two sub-problems, each of which can be handled separately. Then, we adopt an alternating optimization (AO) algorithm with the semidefinite programming (SDP) relaxation. Also, we consider a special case where the circuit power consumption of IoT devices can be neglected. In this case, we derive a closed form solution for the optimal transmission time slots, power allocation and phase shift by the Lagrange dual method. Finally, numerical evaluations validate effectiveness of the proposed scheme, which significantly benefits from the IRS in improving network throughput.

Surface versus Performance Trade-offs: A Review of Layout Techniques

Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.

A Differential Ring Oscillator With Tail Current Source Control Scheme Using N-Type Oxide TFTs

In this article, a voltage-controlled oscillator (VCO) design using n-type metal oxide thin-film transistor (TFT) technology is proposed. The VCO has a differential structure delay cell based on a tail current source control scheme. The circuits were fabricated on a glass substrate using our ITO-stabilized ZnO TFT technology. According to tape-out test results, under a 15-V power supply voltage, the presented VCO can reach a 111.23–171-kHz tuning range, a 4.28-kHz/V tuning sensitivity, and 4% linearity error. When the control voltage changes from 2 to 15 V, the VCO gain range is 177.5–181.9 kHz/V. The phase noise performance was also analyzed. At 150 kHz, the phase noise of the VCO is −74.5 dBc/Hz at a frequency offset of 340 kHz. In addition, the circuit power consumption at the maximum oscillation frequency is 1.5 mW. These results indicate that the VCO can be applied to transparent and flexible sensors and digital signal processor (DSP) electronics with moderate speed requirements.

Energy-Aware Optimization of Zero-Energy Device Networks

In this work, the optimal resource allocation for a zero-energy device network with quality of service requirements is investigated, aiming to minimize the average energy consumption. Under these considerations and accounting for the circuit power consumption of the devices’ hardware, the employment of slotted ALOHA for the uplink data transmission is examined. The derived non-convex optimization problem is transformed into an equivalent convex problem in order to be optimally solved in polynomial time. The solutions of the optimization problem are then given in closed form. Finally, simulation results demonstrate the optimal resource allocation strategy of the zero-energy device network. Notably, taking into account the circuit power consumption leads to a more energy efficient resource allocation scheme.

Datasets design of gate diffusion input based pipeline architecture for numerically controlled oscillator

&lt;span lang="EN-US"&gt;Gate diffusion input (GDI) is a technique, which enables reducing power consumption, area and delay in the digital circuits significantly, at the same time maintains low complexity of the logical design. This paper focuses on the analysis and interpretation of the design and implementation of GDI-based pipeline architecture for numerically controlled oscillator (NCO) using look up table (LUT). Based on the input signal and the alternate signal, this phase separation will separate the phase difference signal. The NCO generates a frequency and phase harmonized output signal with an antecedence fixed frequency clock. The 32-bit counter then compares the current count to the value stored in the compare register. Here the Coherent control comes into picture. It controls the carrier synchronizer by employing data from the 32-bit counter and the obtained data will be saved. It is updated and advanced using the third peer group of frequency synthesis technology. The test outcomes are accompanied with the theoretical concept and reproduced the results. The main objective of GDI-based pipeline architecture for NCO using LUT is to reduce the usage of metal oxide semiconductor field effect transistors (MOSFET’s). NCO is an indispensable component in many digital communication systems linked to modems, software-defined radios, and digital radio, digital down/upconverters for cellular and personal communications service base stations.&lt;/span&gt;

A SMART DESIGN OF A MULTI-DIMENSIONAL ANTENNA TO ENHANCE THE MAXIMUM SIGNAL CLUTCH TO THE ALLOWABLE STANDARDS IN 5G COMMUNICATION NETWORKS

At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell. Since the operating range of 5G communication networks is the same as that of the previous generation, there are no difficulties in using these antennas on 5G communication networks. For any technology, the use of antennas makes it possible to bring data rates closer to maximum values. The new technology that uses separate receivers and transmitters on the same frequency band has further increased the speed of receiving and transmitting data. The design of the existing 4G modem provides for the use of antenna technology. The proposed model provides the construction of a multidimensional antenna. The other passive devices it has a one-way direction, which increases the received signal and reduces the amount of interference from the sides to the back. Therefore, the proposed model possible to increase the signal level to acceptable values, even at unstable reception levels thereby increasing the speed of receiving and transmitting the information. The undoubted advantage of panel antennas is their low cost and exceptional reliability. There is practically nothing in the design that can be broken even when falling from a great height. The only weak point is the high-frequency cable, which can break at the point where it enters the case. To extend the life of the device, the cable must be securely connected.

A low-power conditional analog correlated multiple sampling circuit for low-noise CMOS image sensor

This paper presents a low-power conditional analog correlated multiple sampling (CACMS) circuit based on the passive switched-capacitor (SC) correlated multiple sampling (CMS) technique. The bright pixel output noise is dominated by photon shot noise, which cannot be reduced by CMS within one readout. Therefore, in the CACMS, the CMS operation is performed for a dark pixel output and turned off for a bright pixel output. As a result, the power consumption of the CACMS circuit under the bright pixel output is reduced by 28%. The transfer function and noise reduction effect of the CACMS circuit are also analyzed. The simulation results show that the CACMS circuit achieves an input-referred random noise of 70.3μV rms . In addition, the proposed SC CMS scheme provides designers with a free trade-off on the number of capacitors and the readout time. In the CACMS, the readout time of the SC CMS circuit is reduced by 16.7% at the cost of an extra capacitor.

A Bootstrapped Pseudo Resistor by Reusing OTA-C Filter for Neural Signal Processing

In integrated neural signal monitoring systems, pseudo resistor (PR) is widely used to form very large time constant filters, due to its large impedance within an acceptable die area. However, its linearity (the dependency of the resistance to applied voltage) and impedance are limited by the nonlinear MOS transistors in weak inversion, and suffers from process, voltage and temperature (PVT) variations. In this brief, a PR bootstrapped by reusing the operational transconductance amplifier-capacitor (OTA-C) filter is presented, it substantially increases the impedance and linearity to dynamically support lower frequency neural signal applications. It has no need for extra bias scheme on the gate or bulk, which decreases the circuit complexity, die area and power consumption. The proposed circuit implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process occupies an area of 0.026 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the impedance of the bootstrapped PR is approximately 94 G <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , and the high-pass cut-off frequency is reduced to 0.5 mHz.