Post-distortion Technique Research Articles

Linearization of Radio-Over-Fiber Cloud-RAN Transmitters Using Pre- and Post-Distortion Techniques

This paper proposes a novel approach and apparatus along with its calibration method to use the digital predistortion (DPD) technique in radio-over fiber (RoF) cloud RAN (C-RAN) transmitters that encompass physically spaced central baseband unit (C-BBU) and remote radio head (RRH). The proposed approach requires a calibrated observation path (COP) connecting the RRH to the BBU to mitigate any hardware impairments and distortion using a broadband post-distortion technique. This feedback (FB) link provides on-demand tracking of the change in the downlink (DL) optoelectronic component’s behavior and sends a copy of the radio frequency (RF) output signal to the C-BBU for DPD identification and processing. The proposed technique is experimentally validated using 40 MHz, and 100 MHz LTE-A as DL data signals, while the post-compensation model is built by a 200 MHz LTE-A signal.

A 2.4 mW, +11.3 dBm IIP3 and 17 dB conversion gain CMOS mixer with capacitor cross-coupled and modified post distortion techniques

This paper presents a novel design of a double-balanced folded mixer for ISM applications. By utilizing the capacitor cross-coupled (CCC) topology and a modified post distortion (PD) technique in the transconductance stage, a high linearity mixer is realized with lower power dissipation. The mixer is designed and fabricated in a 0.13-µm CMOS process, operating in the frequency band of 900 MHz. Measurement results indicate a conversion gain of 17 dB, a high third-order input intercept point (IIP3) of 11.3 dBm and a noise figure (NF) of 10 dB. Also, the folded structure allows the mixer to operate under 1.0-V supply voltage with a power dissipation of only 2.4 mW.

Iterative Nonlinearity Mitigation and Decoding for LED Communications

The light-emitting diode (LED) is the major source of nonlinearity in LED communication systems, which needs to be carefully handled to avoid significant performance degradation. Post-distortion is an effective and convenient way to compensate the nonlinear distortion at the receiver side. In this letter, we propose a soft-in-soft-out (SISO) post distorter, which works with an SISO decoder iteratively by exchanging log-likelihood ratios of the coded bits at the receiver. It is demonstrated that the proposed iterative technique can achieve a remarkable performance gain compared to the conventional post-distortion technique in the literature.

A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers

LNAs for wideband receivers usually require a high linearity to protect the desired signals from out-band interference. Active feedback LNAs always suffer from the nonlinear feedback of source follower, and present a poor linearity. In order to solve this problem, a complementary source follower (CSF) is proposed, which utilizes the different characteristic of NMOS and PMOS to linearize the source follower, leading to an improvement of LNA’s IIP3 and IIP2 by about 10 dBm and 21 dBm respectively. In addition, a post-distortion technique is also used on the common source stage, which further enhances the IIP3 by about 2 dBm and IIP2 by 11 dBm. After using the two techniques, the noise figure (NF) does not deteriorate; instead it achieves a 0.3 dB improvement. A prototype is designed in TSMC 0.18 μm CMOS process, and a 14.8 mW power is dissipated from a 1.6 V supply. In typical process corner, across 0.3 to 3.5 GHz, this LNA achieves a 14.6 dB gain, a 2.9 dB minimum NF, and an IIP2 larger than +22 dBm and IIP3 larger than +1.2 dBm.

A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

High-Linearity Drive Amplifier Using Active Local Feedback

A drive amplifier consisting of a cascode amplifier and a local feedback amplifier is proposed to ensure high linearity. The local feedback amplifier with a post distortion technique compensates for the nonlinearity of a common-source stage while maintaining input impedance matching and a reasonable power gain. In addition, a process, supply voltage, and temperature (PVT)-compensated current mirror maintains a high OIP3 point over PVT variations. The theoretical analysis, simulation, and measurement are presented, showing good agreement. Measured results show an OIP3 of 27.2 dBm, OP1dB of 7.8 dBm with a power gain of 7.5 dB at 2.1 GHz, and power consumption of 22.2 mW at 1.8 V. The proposed DA is fabricated using a 0.11 $\mu\text{m}$ CMOS process.

Compact high‐linearity, high‐efficiency complementary metal–oxide–semiconductor power amplifier with post‐distortion lineariser for wireless local area network and Wireless Gigabit Alliance applications

This study proposes a post-distortion linearisation technique for 5 and 60 GHz complementary metal-oxide-semiconductor (CMOS) power amplifiers (PAs). The technique improves the output 1 dB gain compression point (OP 1dB ) and power-added efficiency (PAE) of the PA when the lineariser is turned on. The 5 GHz PA that is fabricated in tsmc TM 0.18 μm CMOS achieves a 16.3 dB gain, a 20 dBm OP 1dB and a 32.6% PAE. The linearised 5 GHz PA improves the OP 1dB and PAE by 2.3 dB and 3.2% as compared to the PA without lineariser. The difference between the OP 1dB and saturated power ( P sat ) is <;0.2 dB. The 60 GHz PA was implemented in a 90 nm CMOS process with a chip area of 0.57 mm 2 . The PA achieves a 14.8 dB gain, a 16.8 dBm OP 1dB with a 16.3% PAE and a 15 GHz 3 dB bandwidth. The power difference between the OP 1dB and P sat is <;0.3 dB. The linearised 60 GHz PA improves the OP 1dB and PAE by 3.2 dB and 5.8% as compared to the PA without lineariser.

High-Precision Motion Detection Using Low-Complexity Doppler Radar With Digital Post-Distortion Technique

Owing to the low complexity and high level of system integration, the quadrature direct-conversion architecture is widely used in Doppler radar for noncontact detection of slow periodic motions such as mechanical vibrations and physiological motions of respiration and heartbeat. However, precise detection of the complete motion pattern has been challenging due to the high-pass characteristics of the ac-coupled baseband circuitry. A few techniques have been proposed to preserve the actual motion pattern in radar sensing based on hardware modifications that add system complexity and cost. In this paper, a digital post-distortion (DPoD) technique is proposed to compensate for the signal distortions in the digital baseband domain. Without any cumbersome hardware modification, the complete pattern of slow periodic motions can be detected using a simple quadrature direct-conversion architecture with ac-coupled baseband. Experimental results show that the proposed Doppler radar with the DPoD technique is robust to compensate signal distortions and can be used for precise detection of slow Doppler motions (near dc) where ac coupling typically attenuates the signal.

Design of 5.5 GHz linear low noise amplifier using post distortion technique with body biasing

A highly linear 5.5 GHz low noise amplifier (LNA) has been designed exploiting source inductive degeneration topology by using post distortion linearization techniques in 0.18 m CMOS technology. This technique improves the input third order intercept point $$(IIP_{3})$$(IIP3) of a low noise amplifier. For enhancing the linearity, this technique used a diode connected MOSFET as IMD sinker and forward body biased which is done in cadence tool. The proposed low noise amplifier achieves high $$IIP_{3}$$IIP3 by using two transistors, main and auxiliary transistors. Also source inductive degeneration topology is employed in the proposed LNA to optimize the noise figure (NF) and $$S_{11}$$S11 at high frequency. In order to reduce power consumption and threshold voltage, Forward Body Biased technique was implemented. In this paper, the first section discusses the most widely used eight linearization techniques and in the second section, the proposed circuit is represented along with its employed topology, techniques and the simulated results. The proposed LNA achieves a simulated third order input intercept $$(IIP_{3})$$(IIP3) of 9.20 dBm while consuming 10.8 mW from a power supply of 1.8 V. it also exhibits a measured gain of 11.34 dB and NF, NF of 2.33 dB.

0.2–4.35 GHz highly linear CMOS balun-LNA with substrate noise optimization

A wideband CG---CS-based balun-LNA is proposed, with high linearity (IIP2 and IIP3) for multi-standard radio applications. By taking advantage of the common-gate transistor's noise and distortion cancellation property in CG---CS-based balun topology, this balun-LNA just focuses on CS-stage's noise and linearity improvement. Post-distortion technique with a p-MOSFET as auxiliary transistor is adopted to suppress the 2nd and 3rd nonlinear terms of the main transistor in CS-stage, and then across 0.2---4.35 GHz, above 34 dBm IIP2 and 7.5 dBm IIP3 with typical process corner is achieved. In addition, in order to reduce the considerable substrate noise from the main transistor in CS-stage, a large resistor is connected between its bulk and source terminal, which reduces the substrate noise contribution from 7.68 to 0.2 % and improves the noise figure (NF) at 1 GHz about 0.38 dB. This balun-LNA was designed in 0.18-μm CMOS, operates from 0.2 to 4.35 GHz, and dissipates 17.8 mW with 1.5-V supply. With typical process corner, this amplifier provides 17.2-dB maximum voltage gain and 2.5---3.2 dB NF.

Adaptive Postdistortion for Nonlinear LEDs in Visible Light Communications

In a visible light communication (VLC) system, the light-emitting diode (LED) is the major source of nonlinearity. The nonlinear effects in the VLC system are different from the conventional wireless communications system. The channel separation in the VLC system is significantly larger than the signal bandwidth; thus, the adjacent channel interference is not an issue. Predistortion technique may not be a cost-efficient approach since it needs additional feedback physical circuits at the transmitter. In this paper, we propose a postdistortion technique to estimate and compensate for the LED's nonlinearity at the receiver. The postdistortion technique only needs some additional computational resources. In addition, the proposed approach significantly improves the error-vector-magnitude and bit-error-rate performance of the VLC system. Simulation results validate the theoretical analysis.

A Differential CMOS Common-Gate LNA Linearized by Cross-Coupled Post Distortion Technique

A linearized differential common-gate CMOS low noise amplifier is proposed. The linearity is improved by a cross-coupled post distortion technique, employing auxiliary PMOS transistors in weak inversion region to cancel the third-order nonlinear currents of common-gate LNA and impair the second-order nonlinear currents of that. The negative conductance characteristic of cross-coupled auxiliary PMOS transistors improves the gain while the resulted NF is little affected. Furthermore, noise contribution and linearity deterioration from the cascode stage is eliminated by an inductor resonating with the parasitic capacitance observed at the source net of the cascode transistor. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 dB and 1.4 dB improvements in the designed frequency band, respectively. The noise figure of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.

6.8 mW 15 dBm IIP3 CMOS common‐gate LNA employing post‐linearisation technique

A linearised differential common-gate CMOS low-noise amplifier (LNA) is proposed. The linearity is improved by a cross-coupled post-distortion technique, employing PMOS in a weak inversion region as an auxiliary field effect transistor to cancel the third-order nonlinear currents of a common-gate LNA and impair the related second-order nonlinear currents. Meanwhile, the resulting noise figure is little affected. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 and 1.5 dB improvements in the designed frequency band, respectively. A NF of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.

A 1.6–9.7 GHz CMOS LNA Linearized by Post Distortion Technique

A linearized ultra-wideband (UWB) CMOS low noise amplifier (LNA) is proposed. The linearity is improved by a post distortion technique, employing PMOS as an auxiliary FET to cancel the second- and the third-order nonlinear currents of common-gate LNA. A three-section band-pass Chebyshev filter is presented for wideband input matching. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and IIP2 have about 9 and 6.9 dB improvements in broad frequency range, respectively. Power gain of 9.6-12.6 dB and noise figure (NF) of 3.9-5.8 dB are obtained in the frequency range of 1.6-9.7 GHz with a power dissipation of 10.6 mW under a 1.8 V power supply.

기지국용 Cross Post-Distortion 평형 선형 전력 증폭기에 관한 연구

본 논문에서는 feedforward와 post-distortion 기법을 이용하여 평형 증폭기 내에서 발생하는 혼변조 왜곡 성분을 제거할 수 있는 새로운 왜곡 상쇄 메커니즘인 cross post-distortion 선형화 기법을 제안한다. 출력 동적 영역과 대역폭 측면에서 제안하는 선형화 방식은 기존의 feedforward 방식에 뒤지지 않는 성능을 가지고 있으면서 상대적으로 높은 효율을 제공한다. 이론적 뒷받침을 위해 제안하는 시스템과 feedforward 방식의 전력 증폭기와 오차증폭기의 전력 용량을 비교 분석하였고, IMT-2000 대역에서 실제 구현을 통하여 이를 실험적으로 뒷받침하였다. 최대 출력 전력 240 W의 기지국용 상용 대전력 증폭기에 적용했을 때, wideband code division multiple access (WCDMA) 4FA 신호에 대하여 평균 출력 전력 40 dBm에서 약 18.6 dB의 개선 효과를 얻었다. 제작된 전력 증폭기는 WCDMA 신호 기준으로 feedforward 방식에 비해 약 2 % 개선된 효율을 보였다. In this paper, we propose a new distortion cancellation mechanism for a balanced power amplifier structure using the carrier cancellation loop of a feedforward and post-distortion technique. The proposed cross post-distortion balanced linear amplifier can reduce nonlinear components as much as the conventional feedforward amplifier through the output dynamic range and broad bandwidth. Also the proposed system provides higher efficiency than the feedforward. The capacities of power amplifier and error power amplifier in the proposed system are analyzed and compared with those of feedforward amplifier. Also the operation mechanisms of the three kind loops are explained. The proposed cross post-distortion balanced linear power amplifier is implemented at the IMT-2000(<TEX>$f_0=2.14\;GHz$</TEX>) band. With the commercial high power amplifiers of total power of 240 W peak envelope power fer base-station application, the adjacent channel leakage ratio measurement with wideband code division multiple access 4FA signal shows 18.6 dB improvement at an average output power of 40 dBm. The efficiency of fabricated amplifier Improves about 2 % than the conventional feedforward amplifier.

A postdistortion receiver for mobile communications

The paper presents a postdistortion receiver, for possible future mobile communication systems, which can potentially increase both the spectral efficiency and the transmitter's power efficiency (especially important for portable units). Postdistortion is a technique, implemented at the base-station receiver, to compensate for AM-AM and AM-PM nonlinearities of a mobile transmitter's amplifier which, if uncompensated, would cause adjacent channel interference. A unique adaptation method is demonstrated to compensate for slow variations in the power amplifier's characteristics without an interruption for a training period. Various aspects of system performances, including SNR and convergence speed, have been simulated. The system performance in fading channel conditions is also considered. The simulation and measured results show that the postdistortion technique can improve the out-of-band emission by up to 20 dB; the corresponding increase in mobile transmitter power efficiency is approximately a factor of 10. The spectral efficiency is approximately increased by 20% with the postdistortion implementation. >