A 2.4 mW, +11.3 dBm IIP3 and 17 dB conversion gain CMOS mixer with capacitor cross-coupled and modified post distortion techniques

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This paper presents a novel design of a double-balanced folded mixer for ISM applications. By utilizing the capacitor cross-coupled (CCC) topology and a modified post distortion (PD) technique in the transconductance stage, a high linearity mixer is realized with lower power dissipation. The mixer is designed and fabricated in a 0.13-µm CMOS process, operating in the frequency band of 900 MHz. Measurement results indicate a conversion gain of 17 dB, a high third-order input intercept point (IIP3) of 11.3 dBm and a noise figure (NF) of 10 dB. Also, the folded structure allows the mixer to operate under 1.0-V supply voltage with a power dissipation of only 2.4 mW.