post-CMOS Process Research Articles

NeuroBus - Architecture for an Ultra-Flexible Neural Interface.

This article presents the system architecture for an implant concept called NeuroBus. Tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible polyimide substrate are connected in a bus-like structure, allowing short connections between electrode and recording front-end with low wiring effort and high customizability. The small size (344 μm × 294 μm) of the ASICs and the ultraflexible substrate allow a low bending stiffness, enabling the implant to adapt to the curvature of the brain and achieving high structural biocompatibility. We introduce the architecture, the integrated building blocks, and the post-CMOS processes required to realize a NeuroBus, and we characterize the prototyped direct digitizing neural recorder front-end as well as polyimide-based ECoG brain interface. A rodent animal model is further used to validate the joint capability of the recording front-end and thin-film electrode array.

Post-CMOS processing challenges and design developments of CMOS-MEMS microheaters for local CNT synthesis

Carbon nanotubes (CNTs) can be locally grown on custom-designed CMOS microheaters by a thermal chemical vapour deposition (CVD) process to utilize the sensing capabilities of CNTs in emerging micro- and nanotechnology applications. For such a direct CMOS-CNT integration, a key requirement is the development of necessary post-processing steps on CMOS chips for fabricating CMOS-MEMS polysilicon heaters that can locally generate the required CNT synthesis temperatures (~650–900 °C). In our post-CMOS processing, a subtractive fabrication technique is used for micromachining the polysilicon heaters, where the passivation layers in CMOS are used as masks to protect the electronics. For dielectric etching, it is necessary to achieve high selectivity, uniform etching and a good etch rate to fully expose the polysilicon layers without causing damage. We achieved successful post-CMOS processing by developing two-step reactive ion etching (RIE) of the SiO2 dielectric layer and making design improvements to a second-generation CMOS chip. After the dry etching process, CMOS-MEMS microheaters are partially suspended by SiO2 wet etching with minimum damage to the exposed aluminium layers, to obtain high thermal isolation. The fabricated microheaters are then successfully utilized for synthesizing CNTs by a local thermal CVD process. The CMOS post-processing challenges and design aspects to fabricate CMOS-MEMS polysilicon microheaters for such high-temperature applications are detailed in this article. Our developed process for heterogeneous monolithic integration of CMOS-CNT shows promise for wafer-level manufacturing of CNT-based sensors by incorporating additional steps in an already existing foundry CMOS process.

Electrical manipulation of a single electron spin in CMOS using a micromagnet and spin-valley coupling

For semiconductor spin qubits, complementary-metal-oxide-semiconductor (CMOS) technology is a promising candidate for reliable and scalable fabrication. Making the direct leap from academic fabrication to qubits fully fabricated by industrial CMOS standards is difficult without intermediate solutions. With a flexible back-end-of-line (BEOL), functionalities such as micromagnets or superconducting circuits can be added in a post-CMOS process to study the physics of these devices or achieve proofs-of-concept. Once the process is established, it can be incorporated in the foundry-compatible process flow. Here, we study a single electron spin qubit in a CMOS device with a micromagnet integrated in the flexible BEOL. We exploit the synthetic spin orbit coupling (SOC) to control the qubit via electric fields and we investigate the spin-valley physics in the presence of SOC where we show an enhancement of the Rabi frequency at the spin-valley hotspot. Finally, we probe the high frequency noise in the system using dynamical decoupling pulse sequences and demonstrate that charge noise dominates the qubit decoherence in this range.

6-20 GHz 30% ScAlN Lateral Field-Excited Cross-Sectional Lamé Mode Resonators for Future Mobile RF Front Ends.

This article reports on 30% scandium-doped AlN (ScAlN) lateral field-excited (LFE) cross-sectional Lame' mode resonators (CLMRs) with unprecedented performance in the 6-20 GHz range. By combining high-crystallinity 30% ScAlN piezoelectric thin films, a lithographic tunability of the resonance frequency, and a simple three-mask post-CMOS compatible fabrication process, we propose a technology platform that can enable the mass production of low-loss, wideband, and compact microacoustic filtering devices spanning a wide spectrum portion on the same chip for the next-generation radio frequency front ends (RFFEs) of handsets. This article demonstrates a successful scaling of the microacoustic technology well beyond the sub-6-GHz fifth-generation (5G) band, as well as the outstanding capabilities of high-crystallinity 30% ScAlN piezoelectric layers in delivering high-quality factor ( Q ) and high-electromechanical coupling ( kt2 ) resonators, notably exceeding the state of the art in terms of relevant figures of merit (FOMs). Furthermore, we experimentally investigate the impact of geometrical parameters, such as tethering configuration and width-over-length ratio on the devices' 3-dB quality factor ( [Formula: see text]), power linearity (PL), and temperature coefficient of frequency (TCF). By adopting a statistical approach for data analysis, we determine the optimal geometry to maximize the Q value. Moreover, we experimentally demonstrate that a fully tethered device's configuration ensures superior PL, lower TCF, and higher device yield and select that as the best design tradeoff between all the variables under consideration. Finally, we discuss a further scaling of LFE CLMRs, both in terms of higher doping levels in the piezoelectric layer, in order to enhance the performance of microacoustic filters, and in terms of higher operation frequencies, in order to reach and cover the mm-wave spectrum.

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

A Miniaturized CMOS-MEMS Amperometric Gas Sensor for Rapid Ethanol Detection

This study presents the design and implementation of a chip-scale amperometric ethanol sensor using the standard commercially available complementary metal oxide semiconductor (CMOS) process together with the post-CMOS micromachining processes. The presented amperometric sensor consists of a suspended plate with a microhole structure as the working electrode, a fully anchored plate with a microhole structure as the counter electrode, and a microcavity as the electrolyte reservoir. The metal and dielectric layers inherent in the standard CMOS process are exploited to realize these structures. The electrode with a microhole structure could enhance its surface area to improve the sensitivity of the sensor. The suspended working electrode covered a thinner Nafion <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text {R}}$ </tex-math></inline-formula> layer could facilitate gas diffusion to shorten the response time of the sensor. To characterize the ethanol sensing, a Ni film is deposited on the working electrode. Measurements indicate the presented sensor has a sensing range of ppm (20–1000 ppm) at room temperature. Moreover, its sensitivity and response time are, respectively, 0.01 nA/ppm and 6 s. The presented design shows the CMOS-MEMS is a promising approach to realize the amperometric ethanol sensor.

A Multimodal and Multifunctional CMOS Cellular Interfacing Array for Digital Physiology and Pathology Featuring an Ultra Dense Pixel Array and Reconfigurable Sampling Rate.

The article presents a fully integrated multimodal and multifunctional CMOS biosensing/actuating array chip and system for multi-dimensional cellular/tissue characterization. The CMOS chip supports up to 1,568 simultaneous parallel readout channels across 21,952 individually addressable multimodal pixels with 13 μm × 13 μm 2-D pixel pitch along with 1,568 Pt reference electrodes. These features allow the CMOS array chip to perform multimodal physiological measurements on living cell/tissue samples with both high throughput and single-cell resolution. Each pixel supports three sensing and one actuating modalities, each reconfigurable for different functionalities, in the form of full array (FA) or fast scan (FS) voltage recording schemes, bright/dim optical detection, 2-/4-point impedance sensing (ZS), and biphasic current stimulation (BCS) with adjustable stimulation area for single-cell or tissue-level stimulation. Each multi-modal pixel contains an 8.84 μm × 11 μm Pt electrode, 4.16 μm × 7.2 μm photodiode (PD), and in-pixel circuits for PD measurements and pixel selection. The chip is fabricated in a standard 130nm BiCMOS process as a proof of concept. The on-chip electrodes are constructed by unique design and in-house post-CMOS fabrication processes, including a critical Al shorting of all pixels during fabrication and Al etching after fabrication that ensures a high-yield planar electrode array on CMOS with high biocompatibility and long-term measurement reliability. For demonstration, extensive biological testing is performed with human and mouse progenitor cells, in which multidimensional biophysiological data are acquired for comprehensive cellular characterization.

CMOS-MEMS Oscillator Architecture and Phase Noise: A Mini-Review

Over the past two decades, the advancement in microelectromechanical systems (MEMS) has been making headway in the development of miniaturized mechanical structures with integrated electronics. By adopting the existing layer in the complementary metal–oxide–semiconductor (CMOS) fabrication platform, the so-called “CMOS-MEMS” technology offers an intrinsic circuit-MEMS integration scheme, paving the way to realize monolithic micromechanical oscillators for frequency control and sensing applications. To enhance the functionality of the oscillator, it is cardinal to understand the secrets behind the resonator and circuit design techniques to generate high spectral purity signals. As the oscillator characteristics heavily depend on the resonator’s motional parameters, the circuit configuration is determined in accordance with the post-CMOS processing technology and the mode shape of the resonator. In this mini-review, we attempt to summarize and appraise studies related to the design and optimization of CMOS-MEMS oscillators and to give directions for future researchers in terms of phase noise.

A Nanoscale Hot-Wire Flow Sensor Based on CMOS-MEMS Technology

In this paper, we proposed an ultrafast and nanoscale hot-wire flow (NHF) sensor implemented in a 0.18 µm complementary metal-oxide-semiconductor microelectromechanical system (CMOS-MEMS) technology. The nanoscale wire was released and reduced in thickness and width by an in-house developed post-CMOS fabrication process, hence the heat conduction loss is greatly suppressed, while the response time of the NHF sensor is significantly improved. Benefiting from the nano size of the hot-wire (a width of 622 nm), the NHF sensor exhibits an ultrafast response time of 30 µs (@ airflow velocity of 0 m/s), a wide flow range of 0–30 m/s, and a cut-off frequency of 21 kHz under the constant temperature (CT) mode. In addition, an equivalent circuit model (ECM) was established in PSPICE to predict the NHF sensor performance, and the theoretical simulation results were in good agreement with the experiment results.

CMOS MEMS Design and Fabrication Platform

This article mainly describes the technology related to the CMOS MEMS process platform provided by the Taiwan Semiconductor Research Institute (TSRI), including the process flow, design verification, back-end dicing, and packaging of the CMOS MEMS integrated sensing single chip. The front-end CMOS processes can be a standard 0.35 or 0.18 µm CMOS process, or even a BCD high-voltage process. Some academic designs also utilize this platform for in-house post-CMOS process. Finally, the article also explains in detail the CMOS MEMS design flowchart and implementation method provided by TSRI.

Design and evaluation of in-plane silicon microneedles fabricated with post-CMOS compatible processes

In this paper, a comprehensive study was carried out on in-plane silicon (Si) microneedles, a useful tool for transdermal drug delivery and sample collection. Microneedles with eleven designs were investigated by post-complementary metal-oxide-semiconductor (CMOS) compatible microfabrication processes and characterized via pricking tests by insertion in chicken breast flesh. Mechanical strength of all designs were also evaluated by theoretical calculation and finite element modeling (FEM) for bending and buckling analysis. To efficiently improve the sharpness and insertion, the wedge-shaped needle tips with thickness determined by Si wafer thickness were sharpened by a wet chemical etching process. Insertion forces recorded from pricking tests and bending and buckling from theoretical calculation and FEM analysis before and after etching were compared. The results showed that the insertion force, free bending force and the maximum buckling force were all reduced and the maximum bending stress were improved after tip sharpening. Furthermore, the buckling safety factor of all eleven designs was great than 1 and the maximum bending stress was less than the fracture strength of Si, indicating that our in-plane Si microneedles are robust enough for insertion into human skin.

Microbolometer with a salicided polysilicon thermistor in CMOS technology.

The metal-type microbolometers in CMOS technology normally suffer low resistivity and high thermal conductivity, limiting their performance and application areas. In this paper, we demonstrate a polysilicon microbolometer fabricated in 0.18 µm CMOS and post-CMOS processes. The detector is composed of a SiO2 absorber coupled with a salicided poly-Si thermistor that has a high resistivity of 1.37×10-4 Ω·cm and low thermal conductivity of 18 W/m·K. It is experimentally shown that the microbolometer with a 40 µm × 40 µm pixel size has a maximum responsibility and detectivity of 2.13×104 V/W and 2.33×109 cmHz1/2/W, respectively. The results are superior to the reported metal-type and diode-type microbolometers in the CMOS process and provide good potential for a low-cost, high-performance, uncooled microbolometer array for infrared imaging applications.

Integration of Ultra-Low Volume Pneumatic Microfluidics with a Three-Dimensional Electrode Network for On-Chip Biochemical Sensing.

This paper reports a novel miniaturized pseudo reference electrode (RE) design for biasing Ion Sensitive Field Effect Transistors (ISFETs). It eliminates the need for post-CMOS processing and can scale up in numbers with the CMOS scaling. The presented design employs silane-mediated transfer of patterned gold electrode lines onto PDMS microfluidics such that the gold conformally coats the inside of microfluidic channel. Access to this electrode network is made possible by using “through-PDMS-vias” (TPV), which consist of high metal-coated SU-8 pillars manufactured by a novel process that employs a patterned positive resist layer as SU-8 adhesion depressor. When integrated with pneumatic valves, TPV and pseudo-RE network were able to bias 1.5 nanoliters (nL) of isolated electrolyte volumes. We present a detailed characterization of our pseudo-RE design demonstrating ISFET operation and its DC characterization. The stability of pseudo-RE is investigated by measuring open circuit potential (OCP) against a commercial Ag/AgCl reference electrode.

CMOS-MEMS technologies for the applications of environment sensors and environment sensing hubs

The booming growth in environmental conditions sensing and monitoring pushes the need of inexpensive environment sensors with small size and low power consumption. The outbreak of COVID-19 further increases the need for fast monitoring of environment conditions. The micro-electrical-mechanical-systems (MEMS) technologies are considered as promising solutions to realize the required environment sensors. The mature complementary metal-oxide-semiconductor (CMOS) process platforms available in many foundries can be extended to fabricate MEMS sensors to offer the advantage of relatively easier commercialization. Moreover, by leveraging the characteristics of CMOS process platforms, the integration of multiple sensors and sensing circuits to form a compact sensing system can also be achieved. This review paper will focus on introducing the miniaturized environmental sensing devices implemented and integrated using the CMOS-MEMS technologies. In general, the CMOS chips for environment sensing are firstly fabricated using the foundry-available CMOS processes, and then the post-CMOS micromachining processes are performed to implement the CMOS-MEMS environment sensors. This paper respectively reviews five different environment sensors (including the infrared, pressure (barometer), humidity/temperature, and gas sensors) using the CMOS-based MEMS technologies. The advantages and design concerns of sensors fabricated by different CMOS and post-CMOS processes are introduced and discussed. Moreover, the CMOS-MEMS environment sensing hub implemented through the monolithic integration of multiple environment sensors is also introduced.

Light Absorption Measurement With a CMOS Biochip for Quantitative Immunoassay Based Point-of-Care Applications.

We present a CMOS biochip-based photometer for quantitative immunoassay diagnostics. The photometer quantifies the concentration of antigens based on light absorption, which allows for a low-cost implementation without expensive optical components. We propose a light controller to lower the start-up and settling time of the light source to 30 seconds, to facilitate fast measurement starts, and to decrease the overall measurement times. The application-specific integrated circuit (ASIC) contains a 6 x 7-sensor array with 100 μm x 100 μm photodiodes that serve as signal transducers. The ASIC was developed in a normal 0.35- μm CMOS technology, avoiding the need for expensive post-CMOS processes. We present our strategy for the assembly of the ASIC and the immobilization of antibodies. For its first time, we demonstrate the quantification of prostate specific antigen (PSA) with an optoelectronic CMOS biochip using this approach. A PSA immunoassay is performed on the top surface of the CMOS sensor array, enzyme kinetics and PSA concentration are measured within 6 minutes with a limit of detection (LoD) of 0.5 ng/ml, which meets clinical testing requirements. We achieve an overall coefficient of variation (CV) of 7%, which is good compared to other point-of-care (PoC) systems.

A Low Impedance CMOS-MEMS Capacitive Resonator Based on Metal-Insulator-Metal (MIM) Capacitor Structure

This letter presents the first nano-gap microelectromechanical systems (MEMS) resonator based on a Metal-Insulator-Metal (MIM) capacitor structure in standard CMOS. We develop an improved mask-less post-CMOS process to chemically remove the thin aluminum copper (AlCu) of the Capacitor-Top-Metal (CTM) with high selectivity to the adjacent materials, yielding a well-defined capacitive transduction gap of only 160 nm. The proof-of-concept resonator is designed in a standard TSMC 180 nm RF CMOS process, with a center frequency of 5.9 MHz, a quality factor of 1,000, and a low motional impedance of 5.7 $\text{k}\Omega $ under a medium dc-bias of 25V. Upon further optimizations, nano-gap CMOS-MEMS resonators based on the proposed CTM-etching technique are promising candidates for fully integrated oscillator applications.

An RF On-Chip Transformer With Fe3O4/GO Nanocomposite Film

In this work, the preparation of Fe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /graphene oxide (GO) nanocomposite and its application in radio frequency (RF) on-chip transformer was investigated. The Fe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /GO nanocomposite was synthesized by using solvothermal method in the presence of GO and integrated into an on-chip transformer by using a novel post-CMOS process. The experimental results show that the Fe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> nanoparticles (with ~13 nm in diameter) are uniformly attached onto the surface of GO and the nanocomposite exhibits typical ferromagnetic behavior. Compared with the identical structural air-core transformer, the inductance (L), quality factor (Q), and coupling coefficient (K) of the device with Fe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /GO nanocomposite film are increased by 28%, 24%, and 11% at 1 GHz, respectively. The enhancement effect of the magnetic film on the RF performance of the transformer has been maintained until 2 GHz. It is believed that Fe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /GO nanocomposite has great potential application in RF on-chip transformers with operation frequency below 2 GHz.

A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors

Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal–oxide–semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.

(Invited) Post-CMOS Compatible Silicon MEMS Nano-Tactile Sensor for Touch Feeling Discrimination of Materials

Semiconductor silicon has realized various kinds of valuable electron devices. CMOS technology is the present standard silicon process to fabricate integrated circuits and systems. Therefore, the word “Post-CMOS” has been an important word which means that the technology makes it possible to fabricate various kinds of MEMS sensors/actuators/passives with highly sophisticated modern CMOS devices. Also, it emphasizes that MEMS devices fabricated by post-CMOS technology has “high compatibility” with “silicon FABs” that are most universal and distributed fabrication facilities in the world. High performance devices and fine microstructures can be fabricated by universal post-CMOS fabrication processes at present.Post-CMOS compatible process is a key technology to realize ultra-high-performance silicon MEMS tactile sensors in this study. We, humans have very sophisticated sense of touch on our fingertip skin, and we can recognize and distinguish various and delicate difference of touch feelings obtained by “sweep motion” of fingertip on various kinds of materials and objects. Our fingertip skin has the highest density of force and vibration (mechanical) receptors like Meissner’s corpuscles and Merkel disks under the surface skin layer where fine pitch patterns of fingerprint are formed on. It is known that human’s fingertip has a very high spatial resolution below 100µm or less, and can recognize existence of 13nm-pitch patterns as reported recently. The high performance of our fingertip sense of touch has never been realized by any tactile sensor device. In order to reproduce artificial sense of touch like the fingertip, very high performances on “spatial resolution” and “input sensitivities” are required to integrate all on a small tactile sensor. Therefore, CMOS-compatible fabrication technology is the most suitable process to fabricate such high-performance tactile sensors with integrated functions.Based on a silicon post-CMOS compatible process, we have realized high performance silicon MEMS tactile sensor called “Nano-tactile sensor”, which is comparable to the performance of fingertip sense of touch. In this tactile sensor device, all the mechanical structures are made from single crystalline silicon which is the active layer of SOI wafers. No elastomer/polymer structures are used in the mechanical sensing structure, and softness and elasticity necessary to tactile sensing are realized by silicon micro mechanical structures. All the fine mechanical movements and sensing circuits with strain-sensitive diffusion resistors (i.e. piezoresistors) are designed by 2D-CAD, and the characteristics can be controlled by layout pattern sizes. The contactor parts of the tactile sensor have curved shape which is similarly designed to the cross-section of a fingerprint, and its suspension springs are designed to have similar spring constant with human’s fingertip skin surface.In the latest version of our “Nano-tactile sensors”, six contactors with fingerprint-like shape are integrated at a pitch of 500µm to get distributed tactile images at a high spatial resolution. The pitch of 500µm corresponds to the average value of human’s fingerprint patterns. Each fingerprint-like contactor reproduces vertical motion (by micro roughness) and horizontal motion (by frictional force) of a fingerprint closely under sweeping motion of fingertip in touch feeling measurement. Spatial resolution of our tactile sensor reaches to sub-micron (200nm) in the finest version, and its force resolution of input reaches below 50µN range. These high performances are enough high to reproduce part of our fingertip sense of touch. The Nano-tactile sensors can get touch feeling waveforms of “hair surface condition”, “skin texture and the condition”, and touch feelings of various kinds of “papers” and “clothes” at a high spatial resolution like our fingertip skin. In the lecture, experimental results of very high-resolution tactile sensing are presented, and their importance and novelty are discussed.Machine learning based on deep neural network (DNN) has become very important for sensing data analysis. We think DNN is very important to understand/reproduce human sense of touch since a trained DNN behaves similarly with human’s senses based on our experiences. Since a lot of sample data are required for such applications, we have developed a measurement system called “Touch-Feeling Scanner”. A number of tactile sensing data can be measured by the touch-feeling scanner integrating a Nano-tactile sensor device. Obtained signals with the scanner were applied to train a DNN for discrimination of different kinds of clothes. 10 kinds of cloth samples have been successfully discriminated at a correct percentage over 95% as an example. Combination of high-resolution Nano-tactile sensors and state-of-the-art machine learning (DNN) is a strong approach to reproduce human fingertip sensation for various valuable applications. Figure 1

(Invited) CMOS-MEMS Based Microgravity Sensor and Its Application

Microelectromechanical systems (MEMS) inertia sensors, such as MEMS accelerometers, are now widely used for a variety of applications in automotive, industrial, healthcare, entertainment, consumer handheld electronics, etc. In this paper, we present our recent progress of a highly sensitive CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson’s disease.(1) Highly sensitive CMOS-MEMS inertia sensor using Au as proof massFigure 1 shows the conceptual image of the CMOS-MEMS inertia sensor. The MEMS structure is fabricated onto standard CMOS wafer using so-called post-CMOS process. Electroplating Au is used. The feature MEMS device is the use of Au proof mass, which contributes to reduce the BN in the inertia sensor. The BN of moving structures determines the sensitivity of MEMS accelerometer. BN is expressed as BN=(4kB T b)1/2/m, where kB , T, b and m are the Boltzmann constant, the absolute temperature, the viscous damping coefficient and the mass of the movable structures of an inertial sensor, respectively. Large the density of the proof mass results in suppressing BN without sacrificing the device footprint.The reason why we use Au as proof masu is that the density of Au is almost an order of magnitude higher than the density of Si that is used as the standard material for proof masses.Today, commercial MEMS inertia sensors accommodate typically more than 1G (1G = 9.8 m/s2: gravitational acceleration). On the other hand, accurate sub-1G to micro-G sensing by using MEMS inertial sensors has potential to realize various unexplored applications, such as precise monitoring of human and non-human objects for healthcare and medical purposes or integrated inertial measurement unit for advanced navigation systems. At present time, 0.1micro-G/Hz^(1/2) Brownian Noise MEMS inertia sensor is available in our research group. Our MEMS sensor has enough performance for detecting microgravity.Figure 2 shows a photo of typical CMOS-MEMS inertia sensor. Control of crystal structure of Au is essential when Au is used as proof mass. Analysis of Au crystal structure and novel Au electroplating technology will be presented at the conference. Also, detail process flow of CMOS-MEMS inertia sensor is presented.(2) Early-stage diagnosis of Parkinson’s diseaseParkinson’s disease is originated from lack of dopamine secretion. Early-stage diagnosis enables the delay of symptom progress and/or the interval extension of Levodopa dosing, resulting in quality-of-life (QoL) improvement of Patient. Parkinson’s disease (PD) is categorized by Hoehn-Yahr (HY) scale from 1(light) to 5 (heavy).We have developed diagnosis of Parkinson’s disease using CMOS-MEMS inertia sensor. So far, walking trajectory and postural abnormality of PD patients and healthy person are analyzed based on machine learning technique. PD patients and healthy individuals can be classified with an accuracy of over 90%.Recently, we have succeeded in detecting the micro musclar sound of the index finger for the first time using a high-sensitivity inertia sensor whose noise level is 10 dB lower than commercially available sensors. These techniques will open a new door of Early-stage diagnosis of Parkinson’s disease. Details of diagnosis of Parkinson’s disease using CMOS-MEMS inertia sensor will be discussed in the presentation.Acknowledgement: This work was financially supported by JST CREST Grant Number JPMJCR1433, Japan, and JSPS KAKENHI Grant Number 19K05232. Figure 1