A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors

Ah-Hyoung Lee,Jihun Lee,Yoon-Kyu Song,Farah Laiwalla,Arto Nurmikko,Jiannan Huang,Vincent Leung

doi:10.3390/mi11100925

Abstract

Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal–oxide–semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.

Highlights

With sustained innovation over decades, the opportunities offered by complementary metal–oxide–semiconductor (CMOS) microelectronics have transformed the electronics of active biomedical implants, taking advantage of the low power consumption, low-cost scalability, and a variety of electronic functions, including systems-on-chip
Cross-sectional images showing the chip being sandwiched by PDMS layers are seen in the side view (a–c) and the angled view (d–f), respectively
We proposed a soft material-based, low stress, scalable post-processing method that allowed for conventional microelectronic fabrication techniques on microscale semiconductor chips carrying extremely delicate CMOS integrated circuits (ICs)

Summary

Introduction

With sustained innovation over decades, the opportunities offered by complementary metal–oxide–semiconductor (CMOS) microelectronics have transformed the electronics of active biomedical implants, taking advantage of the low power consumption, low-cost scalability, and a variety of electronic functions (digital/analog signal processing, data memory, storage, etc.), including systems-on-chip. Once a bare silicon die arrives from a semiconductor fab, a process challenge must be met to enable subsequent post-CMOS processing and packaging steps to complete the functional implant. These might include building biocompatible microelectrodes on contact pads, applying coatings for hermetic sealing, and so on, which typically requires microfabrication processes such as lithography, metallization, etching, and bonding on the CMOS die. As one moves in the future towards ever smaller chips such as the 22-nm transistor node and below [31,32], the smaller die or contact pad size is likely to affect the process yield as finished chips are fragile and difficult to handle, especially when the silicon chip is thinned to around 30 μm, making any post-CMOS process extremely challenging

Methods

Results

Conclusion