Positive Bias Temperature Stress Research Articles

Facile routes to enhance doping efficiency using nanocomposite structures for high-mobility and stable PEALD-ITGO TFTs

In–Sn–Ga–O (ITGO) thin-film transistors (TFTs) fabricated by atomic layer deposition (ALD) are promising candidates for widespread semiconductor applications because of their high mobility and stability. To further improve the device characteristics, the doping efficiency of each cation must be increased. Here, we propose a facile method to enhance the device characteristics using plasma-enhanced ALD-nanocomposite (NC) structures. The deposition of SnO2 materials within the In2O3 layer of the ITGO film with the NC-ITO structure accelerates the reduction of In2O3 (In0: 35.3 % →46.1 %), thereby stabilizing SnO2 (Sn4+: 71.0 % →89.1 %). In addition, this process significantly decreases the fraction of oxygen-related defects (Odefect: 24.0 % →17.6 %) because Sn–O has a substantially higher bond dissociation energy than In–O. Consequently, the ITGO TFT with the NC-ITO active layer exhibits considerable improvements in the electrical parameters, such as an increase in the field-effect mobility from 41.9 to 54.5 cm2/V s and an enhancement in the subthreshold swing from 69.8 to 64.8 mV/decade. In addition, the device shows excellent results for negative bias illumination stress and positive bias temperature stress, with the differences in the threshold voltage shift being −0.22 and + 0.06 V, respectively.

Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors

Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (>32 cm2V−1s−1) along with a current on/off ratio of approximately 108 and a subthreshold swing (SS) value below 0.5 V decade−1 primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

Reliability Engineering of High‐Mobility IGZO Transistors via Gate Insulator Heterostructures Grown by Atomic Layer Deposition

AbstractThe reliability of oxide‐semiconductor (OS) thin‐film transistors (TFTs) is significantly influenced by the gate insulator (GI). During electrical bias stress, the defect sites near the semiconductor/GI interface and/or within the GI may trap electrons, which makes the threshold voltage (Vth) shift toward positive values. On the other hand, carbon (C) or hydrogen (H) atoms may diffuse from the GI into the active layer, and act as shallow donors, which induce negative Vth shifts (ΔVth). In this paper, an in situ atomic layer deposition (ALD)‐based GI heterostructure is introduced, which consists of a stack of two complementary materials, namely Al2O3 and SiO2. Here, a competition occurs between electron trapping in Al2O3 (positive ΔVth) and carrier generation from H atoms in SiO2 (negative ΔVth) which allows the achievement of nearly zero ΔVth under positive bias temperature stress (PBTS). This strategy is successfully applied to a high‐mobility (>50 cm2 Vs−1) ALD‐based indium‐gallium‐zinc oxide (IGZO) device, resulting in a net ∆Vth of −0.02 V under PBTS and drain current variation (∆ID) of +0.49% under constant current stress (CCS). The application of an in situ ALD process thus offers valuable insights to resolve the mobility versus reliability trade‐off in high‐performance oxide TFTs.

Continuous Growth of Crystalline InGaZnO on InLaO by Spray Pyrolysis for High‐Performance Thin‐Film Transistors with Excellent Stability

AbstractInGaZnO (IGZO) based thin film transistors (TFTs) are successfully employed in commercial displays due to their excellent electrical properties but next‐generation displaybackplanes demand higher mobility. A heterojunction structure crystalline oxides can offer superior mobility and stability. Herein, the continuous growth of IGZO is reported on the crystalline InLaO (ILO) layer by spray pyrolysis, which closely resembles the crystalline structure of grown ILO layer. The crystalline structure of the IGZO is confirmed by grazing incidence X‐ray diffraction and high‐resolution transmission electron microscopy. The bilayer IGZO/ILO TFT exhibits remarkable electrical performance, including a high saturation mobility of 55.0 cm2 V−1 s−1, low subthreshold swing of 110 mV dec−1, and high ION/OFF ratio of ≈109 with excellent stability under positive bias temperature stress with In addition, the inverter and ring oscillator based on the IGZO/ILO TFTs demonstrate a high voltage gain of 120 and a low propagation delay of 16.8 ns, respectively. The remarkable performance of bilayer IGZO/ILO TFT by spray pyrolysis is attributed to the In2O3‐like crystalline IGZO grown on ILO film. This leads to reduced lattice mismatch, resulting in minimizing grain boundaries and defects that can hinder electron transport at the interface. The matched crystal structure leads to efficient charge transport at the IGZO and ILO heterojunction, resulting in remarkable TFT performance.

Improved Performance and Bias Stability of Indium‐Tin‐Zinc‐Oxide Thin‐Film Transistors Enabled by an Oxygen‐Compensated Capping Layer

Herein, the effects of oxygen‐compensated capping layer (CCL) on the electrical performance and stability of indium‐tin‐zinc‐oxide (ITZO) thin‐film transistors (TFTs) are investigated. Two different channel structures, namely, single and dual channels, are tested for the ITZO TFTs. The dual‐channel layer is created by depositing an oxygen CCL on the oxygen‐uncompensated channel layer (UCL), while the single‐channel layer consists only of the oxygen UCL. It is found that the oxygen CCL is critical for enhancing the electrical properties of dual‐channel ITZO TFT and its stability under different stress modes such as dynamic stress, positive bias temperature stress, and negative bias illumination stress. The dual‐channel ITZO TFT exhibits a saturation field‐effect mobility of 16.69 cm2 V−1s−1, a threshold voltage of 6.80 V, and a subthreshold swing of 0.22 V dec−1. Furthermore, it is revealed that the higher metal‐oxide concentration and fewer defects in the dual channel lead to enhanced electrical performance and stability of the device. This work demonstrates the potential of utilizing the oxygen CCL for the highly reliable operation of oxide semiconductor TFTs.

Highly Robust Atomic Layer Deposition‐Indium Gallium Zinc Oxide Thin‐Film Transistors with Hybrid Gate Insulator Fabricated via Two‐Step Atomic Layer Process for High‐Density Integrated All‐Oxide Vertical Complementary Metal‐Oxide‐Semiconductor Applications

Highly reliable atomic layer deposition (ALD)‐derived In‐Ga‐Zn‐O thin‐film transistors with high field‐effect mobility (μFE) and hydrogen (H) resistivity are crucial for the semiconductor industry. Herein, a hybrid Al2O3 gate insulator (GI) is proposed that is designed by controlling the plasma‐enhanced ALD and thermal ALD processes in situ to demonstrate robust characteristics. A hybrid GI is applied to the top‐gate geometry of an In0.71Ga0.08Zn0.21O active layer. The optimal device exhibits exceptional electrical characteristics, including a threshold voltage of 0.37 V, μFE of 150.7 cm2 V s−1, subthreshold swing of 64.0 mV decade−1, and hysteresis of 0.02 V. It demonstrates high resistance to H annealing and reliable positive bias temperature stress, as well as changes in VTH shifts of −0.43 and 0.00 V, respectively. The excellent electrical characteristics and high robustness of the device can be attributed to the precise control of H, oxygen, and carbon species within the upper region of the hybrid GI. The achievement of robust device characteristics enables the design of a novel vertical complementary metal‐oxide‐semiconductor inverter that exhibits a voltage gain of 44.7 V V−1 and a noise margin of 87.5% at a 10 V supply voltage.

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors.

Top-gate self-aligned structured oxide thin-film transistors (TFTs) are suitable for the backplanes of high-end displays because of their low parasitic capacitances. The gate insulator (GI) deposition process should be carefully designed to manufacture a highly stable, high-mobility oxide TFT, particularly for a top-gate structure. In this study, a nanometer-thick Al2O3 layer via plasma-enhanced atomic layer deposition (PE-ALD) is deposited on the top-gate bottom-contact structured oxide TFT as the interface tailoring layer, which can also act as the hydrogen barrier to modulate carrier generation from hydrogen incorporation into the active layer of the TFT during the following process such as postannealing. Al-doped InSnZnO (Al/ITZO) with an Al/In/Sn/Zn atomic ratio composition of 1.7:24.3:40:34 was used for high mobility oxide semiconductors, and an Al2O3/Si3N4 bilayer was used for the GI. The degradation issue due to the excellent barrier characteristics of Al2O3 and Si3N4 can be minimized. An oxide TFT fabricated without the interface tailoring layer exhibits conductor-like characteristics owing to the excessive carrier generation by hydrogen incorporation. However, TFTs with additional interface layers exhibit reasonable characteristics and distinct trends in electrical characteristics depending on the thicknesses of the interface layers. The optimized devices exhibit an average turn-on voltage (Von) of -0.31 V with 33.63 cm2/(V s) of high mobility and 0.09 V/dec of subthreshold swing value. The interfaces between the active layer and hydrogen barriers were investigated using a high-resolution transmission electron microscope, contact angle measurement, and secondary ion mass spectroscopy to reveal the origin of the trends in properties between the devices. The top-gate device with a hydrogen barrier using the four-cycle deposition exhibits optimum electrical characteristics of both high mobility and good stability with only a 0.04 V shift of Von under positive-bias temperature stress (PBTS). We realize a high-end, self-aligned TFT with high mobility [34.7 cm2/(V s)] and negligible Von shift of -0.06 V under PBTS by applying a subnanometer hydrogen barrier.

Low-Temperature Solution-Processed HfZrO Gate Insulator for High-Performance of Flexible LaZnO Thin-Film Transistor.

Metal-oxide-semiconductor (MOS)-based thin-film transistors (TFTs) are gaining significant attention in the field of flexible electronics due to their desirable electrical properties, such as high field-effect mobility (μFE), lower IOFF, and excellent stability under bias stress. TFTs have widespread applications, such as printed electronics, flexible displays, smart cards, image sensors, virtual reality (VR) and augmented reality (AR), and the Internet of Things (IoT) devices. In this study, we approach using a low-temperature solution-processed hafnium zirconium oxide (HfZrOx) gate insulator (GI) to improve the performance of lanthanum zinc oxide (LaZnO) TFTs. For the optimization of HfZrO GI, HfZrO films were annealed at 200, 250, and 300 °C. The optimized HfZrO-250 °C GI-based LaZnO TFT shows the μFE of 19.06 cm2V-1s-1, threshold voltage (VTH) of 1.98 V, hysteresis voltage (VH) of 0 V, subthreshold swing (SS) of 256 mV/dec, and ION/IOFF of ~108. The flexible LaZnO TFT with HfZrO-250 °C GI exhibits negligible ΔVTH of 0.25 V under positive-bias-temperature stress (PBTS). The flexible hysteresis-free LaZnO TFTs with HfZrO-250 °C can be widely used for flexible electronics. These enhancements were attributed to the smooth surface morphology and reduced defect density achieved with the HfZrO gate insulator. Therefore, the HfZrO/LaZnO approach holds great promise for next-generation MOS TFTs for flexible electronics.

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility.

Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (VTH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a VTH shift of -0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.

43‐2: Distinguished Student Paper: High‐Performance, Coplanar Amorphous IGZO TFTs by Spray Pyrolysis on PI Substrate for Low Cost Manufacturing of Foldable AMOLED Display

We report a method for low‐cost deposition of bubble‐free and high‐quality amorphous InGaZnO (a‐IGZO) on polyimide (PI) substrate for foldable AMOLED display by spray pyrolysis. The coplanar thin‐film transistor (TFT) with spray‐pyrolyzed (SP) a‐IGZO on PI substrate exhibits VTH of ‐0.8 V, μSAT of 40.95 cm2V‐1s‐1, and SS of 0.18 Vdec‐1 with on/off current ratio of ~108. The TFT shows VTH shift of ‐0.40 V and +0.05 V under tesnsile bending and positive bias temperature stress, respectively. The ring oscillator made of SP a‐IGZO TFTs exhibits an oscillation frequency of 2.38 MHz at VDD of 10 V. The SP a‐IGZO TFT can be used for low‐cost, high‐performance, and flexible display TFT backplanes.

High‐performance, coplanar amorphous InGaZnO thin‐film transistors by spray pyrolysis on polyimide substrate for low‐cost manufacturing of foldable active‐matrix organic light emitting diode display

AbstractWe report a method for low‐cost deposition of bubble‐free, high‐quality amorphous InGaZnO (a‐IGZO) on polyimide (PI) substrate for foldable active‐matrix organic light emitting diode (AMOLED) display by spray pyrolysis. The coplanar thin‐film transistor (TFT) with spray‐pyrolyzed (SP) a‐IGZO on PI substrate exhibits threshold voltage (VTH) of −0.8 V, saturation mobility of 40.95 cm2 V−1 s−1, and subthreshold swing of 0.18 V per decade with on/off drain current ratio of ~108. The high mobility TFT could be achieved using high substrate temperature (350°C) and low contact resistance by NF3 plasma on the SP a‐IGZO. The TFT shows a ΔVTH of −0.4 V when it is bent on a cylinder of 1‐mm radius. The TFT shows the ΔVTH of +0.05 V for positive bias temperature stress at +20 V at 60°C for 1 h. The ring oscillator made of a‐IGZO TFTs exhibits an oscillation frequency of 2.38 MHz at VDD of 10 V with a propagation delay of 9.13 ns per stage. Therefore, the a‐IGZO TFT by spray pyrolysis could be used for low‐cost, high‐performance, and flexible display TFT backplane.

A Comparative Study on Self‐Aligned Top‐Gate Thin‐Film Transistors with Silicon Nitride as the Interlayer

Thin-film transistors (TFTs) with self-aligned top-gate structure are fabricated, in which the source/drain region is pretreated to be highly conductive during the deposition of silicon nitride as the interlayer. Without deteriorating the properties of the device's channel layer, the basic performance of TFTs can be simply controlled by altering the SiH4 flow rate during the deposition of silicon nitride film. Furthermore, the diffusion of hydrogen dissociated from SiH4 precursor, which can passivate the electron traps at the interface between the channel and dielectric layer or in the bulk of the dielectric layer, can significantly improve the positive bias temperature stress stability. The charge trapping mechanism is verified using the stretched-exponential model, and the rising values of the fitting parameters (ΔVth0 and τ) show that the TFTs stability improves as the flow rate of SiH4 rises. This approach can reduce the cost and simplify the manufacturing of thin-film transistors.

Impact of Variant Gate Insulator Fabrication Process on Reliability of Dual-Gate InGaZnO Thin-Film Transistors

The effect of hydrogen diffusion in the bilayer bottom gate insulator (BGI) in dual-gate InGaZnO (IGZO) thin-film transistors (TFT) is investigated. It is discovered that hydrogen diffuses from the first deposited GI, migrates toward the second one, and forms a weak chemical bond with a dangling bond at the interface between the GI and the active layer. The stress condition with a positive gate bias at various temperatures makes the weakly bonded hydrogen break, thereby forming defects that can induce electron trapping in the interface and bulk, causing the threshold voltage to increase. With the rising temperature of positive bias temperature stress (PBTS), more broken bonds appear at the interface, which results in more trapped electrons. Through a charge trapping model and data fitting, the parameter that indicates the quality of the film can be extracted and compared. The trend of degradation between threshold voltage, bond breaking, and defect generation is examined.

High-Performance Amorphous InGaSnO Thin-Film Transistor with ZrAlOx Gate Insulator by Spray Pyrolysis

Here, we report the high-performance amorphous gallium indium tin oxide (a-IGTO) thin-film transistor (TFT) with zirconium aluminum oxide (ZAO) gate insulator by spray pyrolysis. The Ga ratio in the IGTO precursor solution varied up to 20%. The spray pyrolyzed a-IGTO with a high-k ZAO gate insulator (GI) exhibits the field-effect mobility (μFE) of 16 cm2V−1s−1, threshold voltage (VTH) of −0.45 V subthreshold swing (SS) of 133 mV/dec., and ON/OFF current ratio of ~108. The optimal a-IGTO TFT shows excellent stability under positive-bias-temperature stress (PBTS) with a small ΔVTH shift of 0.35 V. The enhancements are due to the high film quality and fewer interfacial traps at the a-IGTO/ZAO interface. Therefore, the spray pyrolyzed a-IGTO TFT can be a promising candidate for flexible TFT in the next-generation display.

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths.

Roles of oxygen interstitial defects located in the In-Ga-Zn-O (IGZO) thin films prepared by atomic layer deposition were investigated with controlling the cationic compositions and gate-stack process conditions. It was found from the spectroscopic ellipsometry analysis that the excess oxygens increased with increasing the In contents within the IGZO channels. While the device using the IGZO channel with an In/Ga ratio of 0.2 did not show marked differences with the variations in the oxidant types during the gate-stack formation, the device characteristics were severely deteriorated with increasing the In/Ga ratio to 1.4, when the Al2O3 gate insulator (GI) was prepared with the H2O oxidants (H2O-Al2O3) due to a higher amount of excess oxygen in the channel. Additionally, during the deposition process of the Al-doped ZnO (AZO) gate electrode (GE) replacing from the indium-tin oxide (ITO) GE, the thermal annealing effect at 180 °C facilitated the passivation of oxygen vacancy and the strengthening of metal-oxygen bonding, which could stabilize the TFT operations. From these results, the gate-stack structure employing O3-processed Al2O3 GI (O3-Al2O3) and AZO GE (OA) was suggested to be most suitable for the device using IGZO channel with a higher In content. On the other hand, the device employing H2O-Al2O3 GI and AZO GE exhibited larger negative shifts of threshold voltage (VTH) under positive-bias-temperature stress (PBTS) condition than the device employing O3- Al2O3 GI and ITO GE due to larger hydrogen contents within the gate stacks. Anomalous negative shifts of VTH were accelerated with increasing the In contents of the IGZO channel. When the channel length of the fabricated device were scaled down to submicrometer regime, the OA gate stacks successfully alleviated the short-channel effects.

14‐2: Student Paper: Enhanced Electrical Characteristics of Low‐Temperature Processed In‐Ga‐Zn‐O Thin‐Film Transistors with Oxygen Scavenging Layer

In this study, the oxygen scavenging layer (OSL) was introduced between channel and gate insulator to improve the electrical characteristics even at 200"C fabrication of amorphous indium‐gallium‐ zinc oxide thin‐film transistors (a‐IGZO TFTs). The OSL is a layer introduced between the channel layer and the gate insulator layer, which is thinly deposited to absorb oxygen in the effective channel of a‐IGZO with annealing process. MgOx was used to make the OSL. The a‐IGZO TFTs with OSL, even if annealed at a low‐temperature of 200°C, exhibit improved electrical characteristics and stability under positive bias temperature stress (PBTS) compared to those without OSL: field‐effect mobility from 8.15 to 16.08 cm2/Vs, subthreshold swing from 0.45 to 0.42 V/decade, on/off current ratio from 3.19 × 108 to 9.53 × 109. A threshold voltage shift under PBTS at 50 °C for 10,000 sec was decreased from + 8.94 V to + 1.98 V. These improvements are attributed to Mg of OSL absorbing oxygen ions in the effective channel layer of a‐IGZO.

Remarkable Stability Improvement with a High‐Performance PEALD‐IZO/IGZO Top‐Gate Thin‐Film Transistor via Modulating Dual‐Channel Effects

AbstractPlasma‐enhanced atomic layer deposition (PEALD)‐based bilayer IZO (back channel)/IGZO top‐gate thin‐film transistors (TFTs) with different IZO and IGZO layer thicknesses are fabricated to evaluate the correlation between thickness and electrical characteristics/reliability caused by dual‐channel modulation. The dual‐channel formed by IZO stacked on the backchannel improves both mobility and reliability of devices as the IZO layer thickness increases. In the TCAD simulation, as the thickness of IZO increases, the current flowing through the IZO channel among the dual channels increases and the main channel transition from IGZO to IZO occurs above a certain IZO layer thickness. The main channel transition to IZO, which has high mobility and is located in the backchannel away from the gate insulator (GI), leads to a mobility increase with a lower threshold voltage (Vth) shift and a remarkable improvement of reliability deteriorated by the GI. As a result, PEALD‐based IZO/IGZO TG TFTs exhibit both high mobility (≈40 cm2 V−1 s−1) and high stability (ΔVth = ‐0.07 V) of a positive bias temperature stress up to 10 800 s. This suggests that ALD‐based dual‐channel regulation by nanoscale thickness control of the stacking oxide semiconductor can overcome the trade‐off between mobility and reliability.

Robust Mobility Enhancement and Comprehensive Reliability Evaluation for Amorphous InGaZnO TFT by Double Layers With Quantum Well Structures

Mobility enhancement is an important research topic for amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) since it is directly related to the device&#x2019;s performance. The double-layer a-IGZO channel with quantum well structure was proposed for mobility enhancement. However, the impact of such double layers with the quantum well structure on a-IGZO TFT reliabilities, i.e., positive bias temperature stress (PBTS) and negative bias temperature illumination stress (NBTIS), is still elusive. In this work, the mobility enhancement by double layers with quantum well structures is proven to be robust in mass production Gen 8.5 line. Then, the a-IGZO TFT under PBTS and NBTIS is investigated systematically. The variations of mobility <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>, subthreshold slope SS, and threshold voltage shift <inline-formula> <tex-math notation="LaTeX">${\Delta {V}_{\text {th}}}$ </tex-math></inline-formula> with PBTS and NBTIS stress time are evaluated and analyzed, respectively. It is shown that the double-layer a-IGZO channel with quantum well structure can sustain as good reliability performance as the reference single-layer device.

Performance Improvement by Double-Layer a-IGZO TFTs With a Top Barrier

The double-layer a-IGZO thin film transistors (DL-TFTs) using a quantum well channel and a top barrier can reduce the subthreshold swing and hysteresis by 0.73 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> and 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> , respectively, in the transfer characteristics using the bottom gate sweep as compared to the single-layer TFTs (SL-TFTs). The wide bandgap barrier on top of the narrow bandgap IGZO channel serves as a protection layer between the IGZO channel and the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> top gate insulator to prevent plasma-induced damage on the IGZO channel caused by the S/D metal etching and the top gate insulator deposition. As for the mobility using the bottom gate operation with the top gate grounded, the DL-TFTs show higher mobility (1.06 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> ) at the room temperature due to less Coulomb scattering caused by the plasma-induced damage for percolation conduction, while the SL-TFTs have higher mobility at low temperatures due to the improved hopping efficiency for thermally activated hopping. The hysteresis is temperature independent down to 160 K, indicating the electrons tunneling between the channel and the top gate insulator is dominant. As for the reliability, DL-TFT has a smaller V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift than SL-TFT under both positive bias temperature stress (PBTS) due to less subgap defect in the channel.