Positive Bias Temperature Stress Research Articles

A study on the high mobility and improved reliability of pr-doped indium zinc oxide thin film transistors

Abstract It is generally accepted that there is a trade-off relationship between mobility and stability for oxide thin film transistor (TFT) devices. Different doping ratios of Ln praseodymium (Pr) into indium (In) zinc (Zn) oxide have been employed as the active layer to get 1# and 2# amorphous oxide semiconductor (AOS) TFTs in this work. The 1#-based TFTs exhibited a high mobility of 49.84 cm2 V−1 s−1 due to the increased concentration of In. By further elevating the Pr doping ratio and adjusting In/Zn ratio of the film, the 2#-based TFT obtained both a good mobility of 26.65 cm2 V−1 s−1, and a promising stability, showing a positive-bias temperature stress stability of ΔV TH = 1.56 V and a negative-bias temperature illumination stress stability of ΔV TH = −1.47 V. It was revealed that the low energy charge transfer state of Pr in 2# film absorbs the visible light, leading to suppressed photo-induced carriers and thus a good illumination reliability of the 2#-based TFTs. In practice, the LCD panel based 2# ACT TFT shows a well stable performance even under 10 000-nit illumination. The result indicates a promising strategy to accelerate the commercialization of AOS TFTs to large-panel display production.

Enhanced Stability Under Positive Bias Temperature Stress in Oxide Thin Film Transistors with Double Gate Structure By Improving Bottom Channel Interface

In this paper, we discuss the causes of reliability degradation in oxide TFTs with a double gate structure and propose methods for improvement. Reducing IGZO deposition power significantly improves PBTS (Positive Bias Temperature Stability) reliability in double gate structures. This improvement is attributed to reduction of excess oxygen defects accumulated at the bottom channel interface, as inferred from the difference in PBTS results for the top single gate and double gate structures

Quantitative Dynamic Evolution of Unoccupied States in Hydrogen Diffused InGaZnSnO TFT under Positive Bias Temperature Stress

Quantitative Dynamic Evolution of Unoccupied States in Hydrogen Diffused InGaZnSnO TFT under Positive Bias Temperature Stress

Plasma-enhanced atomic layer deposition of Sn-doped indium oxide semiconductor nano-films for thin-film transistors

Sn-doped indium oxide (ITO) semiconductor nano-films are fabricated by plasma-enhanced atomic layer deposition using trimethylindium (TMIn), tetrakis(dimethylamino)tin (TDMASn), and O2plasma as the sources of In, Sn and O, respectively. A shared temperature window of 150 °C- 200 °C is observed for the deposition of ITO nano-films. The introduction of Sn into indium oxide is found to increase the concentration of oxygen into the ITO films and inhibit crystallization. Furthermore, two oxidation states are observed for In and Sn, respectively. With the increment of interfaces of In-O/Sn-O in the ITO films, the relative percentage of In3+ions increases and that of Sn4+decreases, which is generated by interfacial competing reactions. By optimizing the channel component, the In0.77Sn0.23O1.11thin-film transistors (TFTs) demonstrate high performance, includingμFEof 52.7 cm2V-1s-1, and a highION/IOFFof ∼5 × 109. Moreover, the devices show excellent positive bias temperature stress stability at 3 MV cm-1and 85 °C, i.e. a minimalVthshift of 0.017 V after 4 ks stress. This work highlights the successful application of ITO semiconductor nano-films by ALD for TFTs.

Temperature Dependent Anomalous Threshold Voltage Modulation of a-IGZO TFT by Incorporating Variant Gate Stresses

Amorphous indium gallium zinc oxide (a-IGZO) has recently made significant advancement as a key material for electronic component design owing to its compatibility with complementary metal oxide semiconductor technologies. A comprehensive analysis of reliability-related issues is required to determine the true potential of a-IGZO-based devices for next-generation electronics applications. To address this objective, we electrically characterize scaled-channel a-IGZO thin film transistors (TFTs) under positive bias (temperature) stress (PB(T)S). Both PBS and PBTS are characterized by positive and negative Vth shift, respectively, during the various gate stresses. In particular, the negative Vth shift is explained by the generation of donor-like traps stimulated by ionization of oxygen vacancy/hydrogen at elevated temperature. The TFTs exhibit relatively decent stability during the PBS operation. The analysis of devices with variant channel dimensions implies that long-channel devices exhibit relatively higher stability and performance compared to the short-channel ones. We also observe that the Vth can be controllably adjusted by employing the top gate (TG) with bottom gate sweep. Moreover, the stress-induced partial recovery mechanism is experimentally observed owing to detrapping of charges. Generally, the reported results infer a perceptive understanding of scaled-channel a-IGZO-TFTs which helps with shaping performance-enhancement strategies.

P‐97: Improved Electrical Performance and Realiability of a‐IGZO TFT by N2O Plasma Treatment Optimization

This study investigates the abnormal reliability degradations observed under positive bias temperature stress (PBTS) in a‐IGZO TFTs treated by N2O plasma treatment and proposes a solution according to the presence of N2O plasma in the subsequent postprocess. In mass manufacture of a‐IGZO TFTs, N2O plasma is usually completely removed during the subsequent post‐plasma treatment processes. However, we maintained the presence of N2O plasma and analyzed its effect on device performance and reliability. While a‐IGZO TFTs fabricated with N2O plasmaremoved during the post‐process exhibited non‐ideal negative Vth shifts under PBTS, the devices fabricated with N2O plasma present during post‐processing showed superior electrical performance and reliability, avoiding the non‐ideal Vth shift phenomenon. This study shows that maintaining N2O plasma during the post‐process is an effective method for ensuring device reliability as well as improved performance of a‐IGZO TFTs in mass production.

P‐11: High Mobility BCE Oxide TFT Technology for Demux Driving Notebook LCD

Ln‐IZO based target was employed to deposit as a channel layer in amorphous Ln‐In‐Zn‐O thin‐film transistors. Here, we use the carrier/barrier bilayer stacked AOS TFTs to improve the mobility and stability. High mobility Ln‐oxide is for better charge transport. The barrier layer is fine‐tuned for better reliability. After optimization of the stacked structure of the active layer and the parameters of the PV SiO2 layer, the devices exhibited superior electric properties. The device shows high mobility (35.4 cm2/Vs) and small voltage shifts (1.1/‐1.5 V) of PBTS (positive bias temperature stress) and NBTIS (negative bias temperature illumination stress). We fabricated a 14 inch notebook liquid crystal display (LCD) with the Demux 1:3 circuit design using the high performance bilayer stacked TFTs.

P‐12: Improve the Reliability of a‐IGZO TFT through Optimizing the Threshold Voltage and Channel Thickness in AMOLED Hybrid Backplane

In the fabrication of flexible a‐IGZO and LTPS thin film transistor (TFT) hybrid backplane, various threshold voltage (Vth) of the a‐IGZO TFT was achieved in this paper by regulating the O2/Ar ratio during the deposition of a‐IGZO film by sputtering. The results show that the Vth increases with the increase of the O2/Ar ratio, and the reliability tests indicate that in a certain range negative adjustment of Vth can significantly improve the positive bias temperature instability (PBTI) of IGZO TFT, and maintain good electrical uniformity. The increase of the O2/Ar ratio reduces the number of oxygen vacancy (Vo) in the a‐IGZO channel, and thereby Vth is positively shifted, which is confirmed by the TCAD simulation. The Vth value can indicate the Vo concentration in a‐IGZO TFT channel partly, and appropriately higher amount of Vo is beneficial to improve the PBTI, which is attributed to Fermi level (EF) shifting closer to conduction band. Raised EF means less unoccupied trap states, resulting in less carrier trapping under PBTI. Furthermore, the research also explores different a‐IGZO channel thicknesses and finds that when the Vth values are similar, thinner channel layers endow a‐IGZO TFT with improved PBTI. By optimizing the Vth and channel thickness, a‐IGZO TFTs with a channel thickness of 25nm and a Vth value of 0.2V have been prepared in a hybrid backplane. Under positive bias temperature stress for 5 hours, the Vth is positively shifted less than 0.5 V, which could lay the foundation for achieving high‐reliability flexible backplane for AMOLEDs.

Facile routes to enhance doping efficiency using nanocomposite structures for high-mobility and stable PEALD-ITGO TFTs

In–Sn–Ga–O (ITGO) thin-film transistors (TFTs) fabricated by atomic layer deposition (ALD) are promising candidates for widespread semiconductor applications because of their high mobility and stability. To further improve the device characteristics, the doping efficiency of each cation must be increased. Here, we propose a facile method to enhance the device characteristics using plasma-enhanced ALD-nanocomposite (NC) structures. The deposition of SnO2 materials within the In2O3 layer of the ITGO film with the NC-ITO structure accelerates the reduction of In2O3 (In0: 35.3 % →46.1 %), thereby stabilizing SnO2 (Sn4+: 71.0 % →89.1 %). In addition, this process significantly decreases the fraction of oxygen-related defects (Odefect: 24.0 % →17.6 %) because Sn–O has a substantially higher bond dissociation energy than In–O. Consequently, the ITGO TFT with the NC-ITO active layer exhibits considerable improvements in the electrical parameters, such as an increase in the field-effect mobility from 41.9 to 54.5 cm2/V s and an enhancement in the subthreshold swing from 69.8 to 64.8 mV/decade. In addition, the device shows excellent results for negative bias illumination stress and positive bias temperature stress, with the differences in the threshold voltage shift being −0.22 and + 0.06 V, respectively.

Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors

Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (>32 cm2 V−1 s−1) along with a current on/off ratio of approximately 108 and a subthreshold swing (SS) value below 0.5 V decade−1 primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

P‐1.9: Enhanced Stability Under Positive Bias Temperature Stress of Ln‐Doped InZnO Thin Film Transistors Fabricated with Back‐channel‐etch Structure

P‐1.9: Enhanced Stability Under Positive Bias Temperature Stress of Ln‐Doped InZnO Thin Film Transistors Fabricated with Back‐channel‐etch Structure

Reliability Engineering of High‐Mobility IGZO Transistors via Gate Insulator Heterostructures Grown by Atomic Layer Deposition

AbstractThe reliability of oxide‐semiconductor (OS) thin‐film transistors (TFTs) is significantly influenced by the gate insulator (GI). During electrical bias stress, the defect sites near the semiconductor/GI interface and/or within the GI may trap electrons, which makes the threshold voltage (Vth) shift toward positive values. On the other hand, carbon (C) or hydrogen (H) atoms may diffuse from the GI into the active layer, and act as shallow donors, which induce negative Vth shifts (ΔVth). In this paper, an in situ atomic layer deposition (ALD)‐based GI heterostructure is introduced, which consists of a stack of two complementary materials, namely Al2O3 and SiO2. Here, a competition occurs between electron trapping in Al2O3 (positive ΔVth) and carrier generation from H atoms in SiO2 (negative ΔVth) which allows the achievement of nearly zero ΔVth under positive bias temperature stress (PBTS). This strategy is successfully applied to a high‐mobility (>50 cm2 Vs−1) ALD‐based indium‐gallium‐zinc oxide (IGZO) device, resulting in a net ∆Vth of −0.02 V under PBTS and drain current variation (∆ID) of +0.49% under constant current stress (CCS). The application of an in situ ALD process thus offers valuable insights to resolve the mobility versus reliability trade‐off in high‐performance oxide TFTs.

Continuous Growth of Crystalline InGaZnO on InLaO by Spray Pyrolysis for High‐Performance Thin‐Film Transistors with Excellent Stability

AbstractInGaZnO (IGZO) based thin film transistors (TFTs) are successfully employed in commercial displays due to their excellent electrical properties but next‐generation displaybackplanes demand higher mobility. A heterojunction structure crystalline oxides can offer superior mobility and stability. Herein, the continuous growth of IGZO is reported on the crystalline InLaO (ILO) layer by spray pyrolysis, which closely resembles the crystalline structure of grown ILO layer. The crystalline structure of the IGZO is confirmed by grazing incidence X‐ray diffraction and high‐resolution transmission electron microscopy. The bilayer IGZO/ILO TFT exhibits remarkable electrical performance, including a high saturation mobility of 55.0 cm2 V−1 s−1, low subthreshold swing of 110 mV dec−1, and high ION/OFF ratio of ≈109 with excellent stability under positive bias temperature stress with In addition, the inverter and ring oscillator based on the IGZO/ILO TFTs demonstrate a high voltage gain of 120 and a low propagation delay of 16.8 ns, respectively. The remarkable performance of bilayer IGZO/ILO TFT by spray pyrolysis is attributed to the In2O3‐like crystalline IGZO grown on ILO film. This leads to reduced lattice mismatch, resulting in minimizing grain boundaries and defects that can hinder electron transport at the interface. The matched crystal structure leads to efficient charge transport at the IGZO and ILO heterojunction, resulting in remarkable TFT performance.

Improved Performance and Bias Stability of Indium‐Tin‐Zinc‐Oxide Thin‐Film Transistors Enabled by an Oxygen‐Compensated Capping Layer

Herein, the effects of oxygen‐compensated capping layer (CCL) on the electrical performance and stability of indium‐tin‐zinc‐oxide (ITZO) thin‐film transistors (TFTs) are investigated. Two different channel structures, namely, single and dual channels, are tested for the ITZO TFTs. The dual‐channel layer is created by depositing an oxygen CCL on the oxygen‐uncompensated channel layer (UCL), while the single‐channel layer consists only of the oxygen UCL. It is found that the oxygen CCL is critical for enhancing the electrical properties of dual‐channel ITZO TFT and its stability under different stress modes such as dynamic stress, positive bias temperature stress, and negative bias illumination stress. The dual‐channel ITZO TFT exhibits a saturation field‐effect mobility of 16.69 cm2 V−1s−1, a threshold voltage of 6.80 V, and a subthreshold swing of 0.22 V dec−1. Furthermore, it is revealed that the higher metal‐oxide concentration and fewer defects in the dual channel lead to enhanced electrical performance and stability of the device. This work demonstrates the potential of utilizing the oxygen CCL for the highly reliable operation of oxide semiconductor TFTs.

Highly Robust Atomic Layer Deposition‐Indium Gallium Zinc Oxide Thin‐Film Transistors with Hybrid Gate Insulator Fabricated via Two‐Step Atomic Layer Process for High‐Density Integrated All‐Oxide Vertical Complementary Metal‐Oxide‐Semiconductor Applications

Highly reliable atomic layer deposition (ALD)‐derived In‐Ga‐Zn‐O thin‐film transistors with high field‐effect mobility (μFE) and hydrogen (H) resistivity are crucial for the semiconductor industry. Herein, a hybrid Al2O3 gate insulator (GI) is proposed that is designed by controlling the plasma‐enhanced ALD and thermal ALD processes in situ to demonstrate robust characteristics. A hybrid GI is applied to the top‐gate geometry of an In0.71Ga0.08Zn0.21O active layer. The optimal device exhibits exceptional electrical characteristics, including a threshold voltage of 0.37 V, μFE of 150.7 cm2 V s−1, subthreshold swing of 64.0 mV decade−1, and hysteresis of 0.02 V. It demonstrates high resistance to H annealing and reliable positive bias temperature stress, as well as changes in VTH shifts of −0.43 and 0.00 V, respectively. The excellent electrical characteristics and high robustness of the device can be attributed to the precise control of H, oxygen, and carbon species within the upper region of the hybrid GI. The achievement of robust device characteristics enables the design of a novel vertical complementary metal‐oxide‐semiconductor inverter that exhibits a voltage gain of 44.7 V V−1 and a noise margin of 87.5% at a 10 V supply voltage.

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors.

Top-gate self-aligned structured oxide thin-film transistors (TFTs) are suitable for the backplanes of high-end displays because of their low parasitic capacitances. The gate insulator (GI) deposition process should be carefully designed to manufacture a highly stable, high-mobility oxide TFT, particularly for a top-gate structure. In this study, a nanometer-thick Al2O3 layer via plasma-enhanced atomic layer deposition (PE-ALD) is deposited on the top-gate bottom-contact structured oxide TFT as the interface tailoring layer, which can also act as the hydrogen barrier to modulate carrier generation from hydrogen incorporation into the active layer of the TFT during the following process such as postannealing. Al-doped InSnZnO (Al/ITZO) with an Al/In/Sn/Zn atomic ratio composition of 1.7:24.3:40:34 was used for high mobility oxide semiconductors, and an Al2O3/Si3N4 bilayer was used for the GI. The degradation issue due to the excellent barrier characteristics of Al2O3 and Si3N4 can be minimized. An oxide TFT fabricated without the interface tailoring layer exhibits conductor-like characteristics owing to the excessive carrier generation by hydrogen incorporation. However, TFTs with additional interface layers exhibit reasonable characteristics and distinct trends in electrical characteristics depending on the thicknesses of the interface layers. The optimized devices exhibit an average turn-on voltage (Von) of -0.31 V with 33.63 cm2/(V s) of high mobility and 0.09 V/dec of subthreshold swing value. The interfaces between the active layer and hydrogen barriers were investigated using a high-resolution transmission electron microscope, contact angle measurement, and secondary ion mass spectroscopy to reveal the origin of the trends in properties between the devices. The top-gate device with a hydrogen barrier using the four-cycle deposition exhibits optimum electrical characteristics of both high mobility and good stability with only a 0.04 V shift of Von under positive-bias temperature stress (PBTS). We realize a high-end, self-aligned TFT with high mobility [34.7 cm2/(V s)] and negligible Von shift of -0.06 V under PBTS by applying a subnanometer hydrogen barrier.

Low-Temperature Solution-Processed HfZrO Gate Insulator for High-Performance of Flexible LaZnO Thin-Film Transistor.

Metal-oxide-semiconductor (MOS)-based thin-film transistors (TFTs) are gaining significant attention in the field of flexible electronics due to their desirable electrical properties, such as high field-effect mobility (μFE), lower IOFF, and excellent stability under bias stress. TFTs have widespread applications, such as printed electronics, flexible displays, smart cards, image sensors, virtual reality (VR) and augmented reality (AR), and the Internet of Things (IoT) devices. In this study, we approach using a low-temperature solution-processed hafnium zirconium oxide (HfZrOx) gate insulator (GI) to improve the performance of lanthanum zinc oxide (LaZnO) TFTs. For the optimization of HfZrO GI, HfZrO films were annealed at 200, 250, and 300 °C. The optimized HfZrO-250 °C GI-based LaZnO TFT shows the μFE of 19.06 cm2V-1s-1, threshold voltage (VTH) of 1.98 V, hysteresis voltage (VH) of 0 V, subthreshold swing (SS) of 256 mV/dec, and ION/IOFF of ~108. The flexible LaZnO TFT with HfZrO-250 °C GI exhibits negligible ΔVTH of 0.25 V under positive-bias-temperature stress (PBTS). The flexible hysteresis-free LaZnO TFTs with HfZrO-250 °C can be widely used for flexible electronics. These enhancements were attributed to the smooth surface morphology and reduced defect density achieved with the HfZrO gate insulator. Therefore, the HfZrO/LaZnO approach holds great promise for next-generation MOS TFTs for flexible electronics.

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility.

Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (VTH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a VTH shift of -0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.

43‐2: Distinguished Student Paper: High‐Performance, Coplanar Amorphous IGZO TFTs by Spray Pyrolysis on PI Substrate for Low Cost Manufacturing of Foldable AMOLED Display

We report a method for low‐cost deposition of bubble‐free and high‐quality amorphous InGaZnO (a‐IGZO) on polyimide (PI) substrate for foldable AMOLED display by spray pyrolysis. The coplanar thin‐film transistor (TFT) with spray‐pyrolyzed (SP) a‐IGZO on PI substrate exhibits VTH of ‐0.8 V, μSAT of 40.95 cm2V‐1s‐1, and SS of 0.18 Vdec‐1 with on/off current ratio of ~108. The TFT shows VTH shift of ‐0.40 V and +0.05 V under tesnsile bending and positive bias temperature stress, respectively. The ring oscillator made of SP a‐IGZO TFTs exhibits an oscillation frequency of 2.38 MHz at VDD of 10 V. The SP a‐IGZO TFT can be used for low‐cost, high‐performance, and flexible display TFT backplanes.