Positive Bias Temperature Instability Stress Research Articles

Anomalous PBTI Effects in N-Type Super Junction under High Gate Voltage Stress

In this work, an anomalous thick oxide-degradation phenomenon in n-type 650-V class super-junction VDMOS transistors is investigated. An unexpected threshold voltage (Vt) decrease was observed with high positive bias temperature instability stress, and the saturation current (IDsat) increases with the stress time. Repeatable and reproducible behaviors have been achieved from multiple devices under test. Based on simulation and experimental results, it is found that the high-energy electrons (caused by high positive gate voltage) in the n-type region at the bottom of the gate oxide layer (top of the N-pillar) are injected into the gate oxide. The high-energy electrons generate electron-hole pairs during the transport to the anode, leaving holes in the gate oxide layer, and thus decreased Vt and increased IDsat. Finally, C-V measurement is also carried out which further confirms the above analysis.

A Comparative Study of AC Positive Bias Temperature Instability of Germanium nMOSFETs With GeO₂/Ge and Si-cap/Ge Gate Stack

AC positive bias temperature instability (PBTI) of germanium nMOSFETs with GeO2/Ge and Si-cap/Ge gate stack was investigated in this brief. AC-DC-AC alternating PBTI stress tests were conducted on both types of devices, the experiment data shows the inserted DC stress phase has little impact on the following AC stress kinetics on GeO2/Ge nMOSFETs but introduce a significant “additional DC generation” on Si-cap/Ge devices. The “additional DC generation” is ascribed to the existence of energy alternating defects (EAD) according to previous studies. Energy distribution under DC and AC stress further demonstrate that EAD are significant on Si-cap/Ge but negligible on GeO2/Ge devices. Effective lifetime prediction is carried out and compared under DC stress after discharge (with a purposely introduced measurement delay) and AC stress on both GeO2/Ge and Si-cap nMOSFETs. The results show GeO2/Ge nMOSFETs’ effective lifetime exhibits no difference under two stress modes, while Si-cap/Ge nMOSFETs’ effective lifetime is underestimated using DC stress after discharge approximation without considering the EAD-induced “additional DC generation”. An extra 0.14V 10-year Vdd design margin can be obtained for Si-cap/Ge nMOSFETs to gain higher performance by taking “additional DC generation” into account. The conclusion is beneficial for process optimization and PBTI reliability improvement of Ge nMOSFETs.

PBTI stress-induced 1/f noise in n-channel FinFET* *Project supported by the National Natural Science Foundation of China (Grant No. 61634008).

The influence of positive bias temperature instability (PBTI) on 1 / f noise performance is systematically investigated on n-channel fin field-effect transistor (FinFET). The FinFET with long and short channel (L = 240 nm, 16 nm respectively) is characterized under PBTI stress from 0 s to 104 s. The 1 / f noise features are analyzed by using the unified physical model taking into account the contributions from the carrier number and channel mobility fluctuations. The I d–V g, I d–V d, I g–V g tests are conducted to support and verify the physical analysis in the PBTI process. It is found that the influence of the channel mobility fluctuations may not be neglected. Due to the mobility degradation in a short-channel device, the noise level of the short channel device also degrades. Trapping and trap generation regimes of PBTI occur in high-k layer and are identified based on the results obtained for the gate leakage current and 1 / f noise.

Reliability of Buried InGaAs Channel n-MOSFETs With an InP Barrier Layer and Al2O3 Dielectric Under Positive Bias Temperature Instability Stress

The positive bias temperature instability (PBTI) reliability of buried InGaAs channel n-MOSFETs with an InP barrier layer and Al2O3 gate dielectric under medium field (2.7 MV/cm) and high field (5.0 MV/cm) are investigated in this paper. The Al2O3/InP interface of the insertion of an InP barrier layer has fewer interface and border traps compared to that of the Al2O3/InGaAs interface. The subthreshold slope, transconductance, and shift of Vg are studied by using the direct-current Id-Vg measurements under the PBTI stress. The experimental results show that the degradation of positive ΔVg under the medium field stress is mainly caused by the acceptor trap, while the donor trap under the high field stress become dominant in the subthreshold region, which leads to the negative shift in Vg. The generation of acceptor trap are attributed by the InP barrier layer in the buried InGaAs channel n-MOSFETs, resulting that the part of recoverable donor trap has been neutralized under the high field stress. Compared to the surface InGaAs channel n-MOSFETs under PBTI stress, the low leakage current can be achieved in the buried InGaAs channel n-MOSFETs with an InP barrier layer.

Investigation of Positive Bias Temperature Instability Characteristics of Fully Depleted Silicon on Insulator Tunneling Field Effect Transistor with High-k Dielectric Gate Stacks.

The positive bias temperature instability (PBTI) characteristics of fully depleted silicon on insulator (FD-SOI) tunneling field effect transistor (TFET) are investigated in comparison with those of metal oxide semiconductor field effect transistor (MOSFET) fabricated with the same technology process. Unlike some of the previously reported studies, in which the PBTI lifetime of TFET is much longer than that of MOSFET, in this study, the PBTI lifetime of TFET is found to be shorter than that of MOSFET. This result is very interesting, because degradation of electrical parameters of TFET is mainly affected by local traps near the source junction rather than global traps in the channel region. Large degradation of the electrical parameters of TFET due to PBTI stress would result from large fluctuation of the vertical electric field caused by traps near the source junction. This electric field fluctuation near the local region in TFET has more impact on electrical parameter degradation than channel conductivity fluctuation in MOSFET. Therefore, to improve the reliability characteristics of TFET, evaluation of PBTI characteristics and improvement of the quality of gate oxide near the source junction are essential.

Interface state degradation during AC positive bias temperature instability stress

The reliability of a bulk fin field-effect transistor (FinFET) with a high-k dielectric/metal-gate stack has been investigated by comparing the effects of DC and AC stresses. It is well known that the relaxation during the off-cycle of the AC stress decreases the Vth shift and enhances the device lifetime due to electron detrapping from the high-k dielectric. We found that the relaxation in the interface traps is significantly weaker than that of bulk traps during the unipolar and bipolar AC stresses. The weak recovery is attributed to the concurrent interface state generation during a positive-bias temperature instability (PBTI) stress. Eventually, the interface traps became a major source of the device drift (over 60%) at the high temperature of 400 K. This finding suggests that a new strategy is required to address the PBTI reliability focusing on the residual interface states as well as the bulk trapping, particularly at a high temperature.

Threshold Voltage Instability in GaN HEMTs With p-Type Gate: Mg Doping Compensation

In this letter, we present an analysis of the threshold voltage shift induced by positive bias temperature instability stress in GaN-based power HEMTs with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, we show the positive effect of the magnesium compensation process in the p-GaN layer on the long-term threshold voltage instability. When a relatively high positive bias is applied to the gate (Schottky junction reverse-biased), holes are generated by impact ionization in the high-field depleted p-GaN region, then accelerated toward the AlGaN layer. The high-energy holes, combined with the high temperature effects, create defects in the AlGaN or at its interface with p-GaN, causing a long-term positive threshold voltage shift. A process variation in the p-GaN layer is introduced which promotes a wider depletion region near the Schottky interface with the metal, lowering the electric field and reducing the generation of holes due to impact ionization. As a result, the long-term threshold voltage instability is improved without altering the dc transistor parameters, such as threshold voltage, trans-conductance, and subthreshold slope.

Two-step degradation of a-InGaZnO thin film transistors under DC bias stress

A unified explanation is proposed to consistently explain the two-step degradation of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) under DC positive bias temperature instability (PBTI) stress without or with different drain stress voltages (Vds). For PBTI stress without stress Vds, this initial negative Vth shift is believed to be induced by donor-like defect states corresponding to H2O molecule and intrinsic defects, while for PBTI stress with stress Vds, the negative shift is believed to be induced by donor-like defect states corresponding to oxygen vacancies. The gate-bias-induced electron trapping mechanism is responsible for positive Vth shift. These transitions from negative to positive Vth shift are resulted from the competition between the donor-like states creation and electron trapping.

PBTI in GaN-HEMTs With p-Type Gate: Role of the Aluminum Content on $\Delta V_{\mathrm {TH}}$ and Underlying Degradation Mechanisms

In this paper, we present an experimental analysis of the degradation induced by positive bias temperature instability stress in GaN-based power high electron mobility transistors with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, the role of the aluminum content (Al%) in the AlGaN barrier layer on the threshold voltage degradation is investigated by means of constant voltage stress measurements. This has been performed for different process conditions with varying Al content. Main results in this paper demonstrate that when a relatively large positive bias is applied on the gate, two competing trapping mechanisms take place in the AlGaN barrier layer or at the p-GaN/AlGaN interface causing ${V}_{\text {TH}}$ instability. First, an aluminum independent hole trapping mechanism, caused by elastic tunneling from p-GaN valence band (2-D hole gas), leads to a relatively short-time and recoverable negative ${V}_{\text {TH}}$ shift. In the second step, defect creation occurs. These additional defects are filled with electrons and cause a permanent or slowly recoverable positive ${V}_{\text {TH}}$ degradation. The amount of defect creation was dependent on the Al% in the barrier.

Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and AlO Dielectric**Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003, the National Natural Science Foundation of China under Grant No 61504165, and the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metal-oxide-semiconductor field-effect transistor with a InGaP barrier layer and AlO dielectric is investigated. Well behaved split C–V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InGaP barrier layer. The direct-current – measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive in the on-current region. The – degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced acceptor traps contain both permanent and recoverable traps. Compared with surface channel InGaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

InGaAs QW-MOSFET Performance Improvement Using a PEALD-AlN Passivation Layer and an <italic>In-Situ</italic> NH3Post Remote-Plasma Treatment

In this letter, we report on the impact of a PEALD-AlN interfacial passivation layer (IPL) and an in-situ NH3 post remote-plasma (PRP) treatment onto InGaAs quantum-well MOSFETs with Ti/HfO2/InGaAs gate stack. Transistors with gate lengths down to 80 nm have been fabricated and characterized. Due to the excellent interfacial quality of HfO2/AlN/InGaAs, the subthreshold swing and the peak effective channel mobility have been improved to 93 mV/decade and 4253 cm2/Vs, respectively. The drain current has also shown a 4.6-fold enhancement, to 164 mA/mm ( ${I}_{ \mathrm{\scriptscriptstyle OFF}} \,\,{=}\,\,{100}$ nA/ $\mu \text{m}$ and ${V} _{\mathrm {DD}} \,\,{=}\,\,{0.5}$ V), compared with the HfO2 control device. The results also show that the HfO2/AlN device exhibits better immunity to short-channel effects (SCEs) than the HfO2 control device. Furthermore, during positive bias temperature instability stress, a smaller ${V}_{\mathrm {TH}}$ and a lower ${G}_{\mathrm {m}}$ were observed for the sample with an AlN IPL and NH3 PRP treatment, indicating that it is more reliable than the sample without any IPL or plasma treatment.

Positive-Bias Temperature Instability Improvement of Poly-Si Thin-Film Transistor With HfO2 Gate Dielectric by Ammonia Plasma Treatment

In this paper, positive-bias temperature instability (PBTI) stress with different stress voltage at $T = 125~^{\circ }\text{C}$ is executed on the high-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with HfO2 gate dielectric and ammonia (NH3) plasma surface treatment. The NH3 plasma surface treatment on the poly-Si TFT with HfO2 gate dielectric can significantly decrease the threshold voltage ( $V_{\mathrm{ TH}}$ ) approximately −1.86 V, reduce the subthreshold slope (S.S.) approximately −88 mV/decade, enhance the transconductance ( $G_{m}$ ) approximately $2.4\times $ , and driving current ( $I_{\mathrm{ drv}})$ approximately 2.34. In addition, the device degradation after PBTI stress with stress voltage $V_{G} - V_{\mathrm{ TH}} = 7$ V for 1000 s at $T = 125~^{\circ }\text{C}$ can also be improved after the NH3 plasma surface treatment, such as the suppressing of $V_{\mathrm{ TH}}$ shift from 2.063 to 0.617 V, S.S. degradation quantity from 0.284 V/decade to 0.172 V/decade, and $I_{\mathrm{ drv}}$ reduction from −77% to −44%. The improvement of the PBTI of poly-Si TFTs with NH3 plasma surface treatment is attributed to the suppression of oxide charge trapping effect and the degradation of interface state density ( $N_{\mathrm{ it}}$ ) and grain boundary trap state density ( $N_{\mathrm{ GB}}$ ).

A Comparative Study of NBTI and PBTI Using Different Experimental Techniques

Degradation in planar high-k metal gate p- and n-channel MOSFETs, respectively, under negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) stress is studied using different characterization methods. Ultrafast measure stress measure (UF-MSM) method with a measurement delay of a few microseconds is used to characterize the threshold voltage shift ( $\Delta V_{T}$ ). Gated-diode or direct current IV is used to directly estimate the trap generation (TG) during BTI, after correcting for the measurement inconsistencies. BTI experiments are performed under DC stress at different stress bias ( $V_{\mathrm {G-STR}}$ ) and temperature ( ${T}$ ) values also under AC stress at different pulse duty cycle (PDC) and frequency ( ${f}$ ) values. Measured $\Delta V_{T}$ as well as TG show remarkable similarities between NBTI and PBTI stress, under both DC and AC stress. It is shown that TG dominates NBTI and PBTI degradation under both DC and AC stress.

Electrical Analysis and PBTI Reliability of In0.53Ga0.47As MOSFETs With AlN Passivation Layer and NH3Postremote Plasma Treatment

We report a notable improvement in performance, electron transport, and reliability of HfO2/In0.53Ga0.47As nMOSFETs using a plasma-enhanced atomic layer deposition AlN interfacial passivation layer (IPL) and NH3 postremote plasma treatment (PRPT). The interface state density $D_{{\mathrm {it}}}$ decreased by approximately one order of magnitude from $6.1 \times 10^{{\mathrm {12}}}$ to $4 \times 10^{{\mathrm {11}}}$ cm $^{{\mathrm {-2}}}$ eV $^{{\mathrm {-1}}}$ , and the border trap density $N_{{\mathrm {bt}}}$ also declined ten times from $2.8 \times 10^{{\mathrm {19}}}$ to $2.7 \times 10^{{\mathrm {18}}}$ cm $^{{\mathrm {-3}}}$ , resulting in the reduction of the accumulation frequency dispersion and eliminate the inversion hump in C–V characteristics, and thus improves the device performances. Furthermore, positive bias temperature instability stress indicates that the sample with the AlN IPL and NH3 PRPT is more reliable than the sample without any IPL and plasma treatment. During PBT stress, a smaller threshold voltage shift and less transconductance degradation were observed for the sample with the AlN IPL and NH3 PRPT. In addition, the maximum overdrive voltage for a ten-year operating lifetime increased from 0.19 to 0.41 V.

Bias Temperature Instabilities for High-kHfO2LTPS-TFTs With Dual Plasma Treatment

This study is the first to investigate different reliability mechanisms of high-performance low-temperature polycrystalline silicon thin-film transistors (TFTs) with a $\hbox {HfO}_{2}$ gate dielectric before and after dual plasma treatment (DPT) under various bias temperature instability (BTI) stresses. DPT samples under positive bias temperature instability (PBI) and negative bias temperature instability (NBI) stresses exhibited different degradation phenomena because of the negative polarity trapped oxide charges and positive fixed oxide charges (Si+), respectively. In addition, experimental data exhibited better reliability immunity for PBI stress than NBI stress after DPT. Furthermore, we raised the temperature to clearly observe the effect of the PBTI stress analysis for samples with and without DPT. Extracted measurement results showed distinct time evolutions of the interface state densities (Nit) for samples with and without DPT, revealing the different mechanisms of Nit generation with and without DPT. Finally, we proposed a novel reliability mechanism called the quasi reaction-diffusion model to explain the generation of $\Delta\hbox {N}_{\rm it}$ , which also explains the unclear phenomena of mobility boost.

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process**Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (Ea) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.

An Experimental Perspective of Trap Generation Under BTI Stress

A gated-diode or direct current IV method is used to characterize trap generation (TG) under negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) stress in different planar high-k metal gate p-channel and n-channel MOSFETs, respectively. After correction of the measurement delay, very similar time (tSTR), voltage (VG,STR), temperature (T), AC pulse duty cycle, and frequency ( f ) dependence of TG is seen for NBTI and PBTI. Measured TG shows power-law time dependence with a time exponent of n ~ 0.16 for NBTI and PBTI and for DC and AC stress. Uncoupled nature of voltage acceleration (Γ) and T activation (EA) is seen. Interlayer scaling has a similar impact on EA and Γ for NBTI and PBTI. However, the physical location of TG is shown to be different for NBTI and PBTI stress.

Impact of Varying Indium(x) Concentration and Quantum Confinement on PBTI Reliability in InxGa1-xAs FinFET

In this letter, we present a comparative study of positive bias temperature instability (PBTI) reliability in InxGa1-xAs FinFET with varying Indium ( $x=0.53$ , 0.70) percentage and quantization [bulk, quantum well (QW)]. Due to lower effective transport mass and higher injection velocity, In0.7Ga0.3As QW FinFET provides better performance than In0.53Ga0.47As bulk FinFET. However, stronger quantization lowers the effective barrier height between the carriers and defect density in the oxide causing degraded PBTI reliability in the former. Our preliminary PBTI stress study shows that In0.7Ga0.3As QW FinFETs may need to operate at a gate overdrive of 0.1 V (i.e., near threshold operation) to meet 10 years of reliability specifications at 85 °C.

Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process

Positive bias temperature instability (PBTI) characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 eV, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.

Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO2 nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime tL=1.64×1010s, which agreed well with the tL=1.92×1010 s measured at low gate stress voltage, whereas the conventional model overestimates tL by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating tL of high-k nMOSFETs.