Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and AlO Dielectric**Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003, the National Natural Science Foundation of China under Grant No 61504165, and the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of

Abstract

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metal-oxide-semiconductor field-effect transistor with a InGaP barrier layer and AlO dielectric is investigated. Well behaved split C–V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InGaP barrier layer. The direct-current – measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive in the on-current region. The – degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced acceptor traps contain both permanent and recoverable traps. Compared with surface channel InGaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.