Abstract
A gated-diode or direct current IV method is used to characterize trap generation (TG) under negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) stress in different planar high-k metal gate p-channel and n-channel MOSFETs, respectively. After correction of the measurement delay, very similar time (tSTR), voltage (VG,STR), temperature (T), AC pulse duty cycle, and frequency ( f ) dependence of TG is seen for NBTI and PBTI. Measured TG shows power-law time dependence with a time exponent of n ~ 0.16 for NBTI and PBTI and for DC and AC stress. Uncoupled nature of voltage acceleration (Γ) and T activation (EA) is seen. Interlayer scaling has a similar impact on EA and Γ for NBTI and PBTI. However, the physical location of TG is shown to be different for NBTI and PBTI stress.
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