Positive Bias Temperature Instability Degradation Research Articles

Performance and reliability improvement in Ge(1 0 0) nMOSFETs through channel flattening process

The impact of channel flattening process, dozen digital etching (DDE), which is several dozen cyclic treatments of plasma oxidation and oxide wet etching, on device performance and reliability of Ge(1 0 0) nMOSFETs has been systematically investigated. It was found that DDE improves not only electron mobility but also Positive Bias Temperature Instability (PBTI). The PBTI degradation was found related to the pre-existing bulk traps inside gate stack instead of interfacial traps generation. DDE is considered a promising technique for constructing ultra-scaled Ge 3D channel architecture such as nanowire or nanosheet for high performance CMOS devices.

The role of the disordered HfO2 network in the high-κ n-MOSFET shallow electron trapping

Current understanding of the bias temperature instability degradation usually comprises two parts: (1) shallow-level component that can recover within a short time and (2) deep level traps that the emission time of the trapped carrier is extremely long. Prevenient studies of the positive bias temperature instability degradation in the high-κ n-MOSFET indicate that oxygen vacancy (VO) is the dominant defect type that responds for the shallow electron trapping. However, recent experimental results reveal that the VO defect density required to accommodate the experimental measured recoverable threshold voltage degradation (ΔVth) is much higher than that of the reasonable atomic structure in the amorphous HfO2. On the other hand, investigations on the disordered Hf-O-Hf network in the amorphous HfO2 reveal their capabilities as charge trapping centers; therefore, in this work, atomic simulation work is performed, and our results show that the disordered Hf-O-Hf networks can act as effective electron capture centers with shallow levels near the Si conduction band. Moreover, the high density of the stretched Hf-O-Hf networks in the amorphous HfO2 also significantly enriches the shallow electron traps in the oxide.

Investigation of PBTI Degradation in Nanosheet nFETs With HfO2 Gate Dielectric by 3D-KMC Method

Stacked nanosheet transistor (NST) has been regarded as a promising candidate to enable scaling beyond FinFET for the sub-5 nm technology node due to the superior performance. However, reliability optimization from the physical perspective, which is essential for the guideline of NST cell design, still remains unclear. In this paper, we investigate positive bias temperature instability (PBTI) degradation in the ultra-scaled n-type NST with HfO2 gate dielectric by three-dimensional-kinetic Monte Carlo method considering multiple microscopic mechanisms. Gate voltage bias and temperature dependent PBTI characteristics are presented. Furthermore, the impacts of width (Wsh) and height (Hsh), key design parameters for NST, on PBTI degradation and threshold voltage shift (ΔVth) variation are evaluated. The results show that with the larger Wsh/Hsh, PBTI becomes severer but suffers less variation and the high temperature enlarges ΔVth variation. In the case of same device perimeter, PBTI is more sensitive to the narrow Hsh side.

The threshold voltage degradation model of N Channel VDMOSFETs under PBT stress

With the voltage increasing in DC power systems, positive bias temperature instability (PBTI) induced gate oxide degradation of commercial n-channel power vertical double diffused MOSFETs (VDMOSFETs) has been greatly enhanced recently. However, it is not mature in some aspects, e.g., parametric models of PBTI and the turn-around phenomenon are rarely studied. Aiming at these disadvantages, the experimental study and the argument are proposed in this paper. First, the simulation was used to identify and verify the threshold voltage as the characteristic parameter and the accelerated experiment test was conducted to collect data for degradation modeling. Then, a Power law-Arrhenius combined model was adopted in the degradation model to take into account the electrical and thermal influence. Besides that, a two-phase PBTI degradation model was presented, which can describe the turn-around phenomenon. Moreover, the comparison of the estimated remaining useful life (RUL) results with the experimental data verified the accuracy of the developed model.

Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and AlO Dielectric**Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003, the National Natural Science Foundation of China under Grant No 61504165, and the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metal-oxide-semiconductor field-effect transistor with a InGaP barrier layer and AlO dielectric is investigated. Well behaved split C–V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InGaP barrier layer. The direct-current – measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive in the on-current region. The – degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced acceptor traps contain both permanent and recoverable traps. Compared with surface channel InGaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

A Comparative Study of NBTI and PBTI Using Different Experimental Techniques

Degradation in planar high-k metal gate p- and n-channel MOSFETs, respectively, under negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) stress is studied using different characterization methods. Ultrafast measure stress measure (UF-MSM) method with a measurement delay of a few microseconds is used to characterize the threshold voltage shift ( $\Delta V_{T}$ ). Gated-diode or direct current IV is used to directly estimate the trap generation (TG) during BTI, after correcting for the measurement inconsistencies. BTI experiments are performed under DC stress at different stress bias ( $V_{\mathrm {G-STR}}$ ) and temperature ( ${T}$ ) values also under AC stress at different pulse duty cycle (PDC) and frequency ( ${f}$ ) values. Measured $\Delta V_{T}$ as well as TG show remarkable similarities between NBTI and PBTI stress, under both DC and AC stress. It is shown that TG dominates NBTI and PBTI degradation under both DC and AC stress.

Insight Into Electron Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging

The access transistor of SRAM can suffer both positive bias temperature instability (PBTI) and hot carrier aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4 eV below conduction band ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{c}$ </tex-math></inline-formula> ) of high-k dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs’ peak is 0.2 eV deeper than that of preexisting ETs. In contrast with the power law kinetics for charging the preexisting ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modeling HCA. A cyclic and antineutralization ETs model is proposed to explain PBTI and HCA degradation, which consists of preexisting cyclic ETs, generated cyclic ETs, and antineutralization ETs.

Early detection and prediction of HKMG SRAM HTOL performance by WLR PBTI tests

With technologies scaling down to 28nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO2 film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times.

Mitigating the Impact of NBTI and PBTI Degradation

Modern CMOS devices encounter a major problem that alters the threshold voltages of the NMOS and PMOS. Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) are common ageing phenomena observed in PMOS and NMOS devices, respectively. Due to operating temperature and stress time, NBTI and PBTI create a decrease in drain-to-source current and an increase in propagation delay. Threshold voltage is an important parameter due to exponential dependence on delay and leakage power. Threshold voltage variations produce adverse effects on operation frequency. These phenomena accrue in pull-up/pull-down transistors in stack and vastly degrade CMOS performance. This paper discusses the various factors responsible for NBTI and PBTI and the challenges associated with modeling these effects due to the recovery mechanism exhibited by the transistors when the stress is removed. Therefore, we propose an algorithm to reduce the effects of NBTI and PBTI that will reduce the stress time for each transistor through the relative repositioning of the transistors based on the signal probability.

Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process

Positive bias temperature instability (PBTI) characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 eV, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.

Saturation of threshold-voltage shift during positive bias temperature instability in HfSiON/SiO2 n-channel MOSFET and its effect on device lifetime evaluation

This paper investigates the saturation of threshold-voltage shift ΔVth of HfSiON/SiO2 n-channel MOSFETs (nMOFSETs) under positive bias temperature instability (PBTI) and proposes an empirical PBTI degradation model that can predict operational lifetime tL accurately. Experimental results indicate that secondary-hole trapping occurred in the bulk dielectric due to hole injection at the anode after electron trapping in the initial bulk trap. This secondary-hole trapping causes a decrease in the time exponent n of the power law ΔVth ∝ tn as the gate stress voltage Vg,str increases. This dependency of n on Vg,str results in overestimation of tL when it was estimated using the conventional method which assumes a constant value of n. An empirical model that considers the effect of Vg,str on n is proposed; this model predicted operational tL = 2.6 × 105 s, which agreed well with experimentally-measured tL = 3.9 × 105 s.

Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO2 nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime tL=1.64×1010s, which agreed well with the tL=1.92×1010 s measured at low gate stress voltage, whereas the conventional model overestimates tL by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating tL of high-k nMOSFETs.

HKMG CMOS technology qualification: The PBTI reliability challenge

We present a brief overview of Positive Bias Temperature Instability (PBTI) commonly observed in n-channel MOSFETs with SiO2/HfO2/TiN dual-layer gate stacks when stressed with positive gate voltage at elevated temperatures. We review the origin and present understanding of the characteristics of oxide traps that are responsible for the complex behavior of threshold voltage stability. We discuss the various physical mechanisms that are believed to govern the transient charging and discharging of these traps as the backbone of the models that have been proposed for PBTI degradation and recovery. Next we review the state-of-the-art in PBTI characterization and we present some of the key stress results on both the device as well the circuit level. Special emphasis is given on the open PBTI issues that need to be carefully addressed for a robust reliability methodology that accurately predicts PBTI lifetimes. Finally we mention some of the gate stack scaling effects on PBTI.

Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-$\kappa$ Metal-Gate Devices

The threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) drifts induced by negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> drifts degrade SRAM cell stability, margin, and performance, and may lead to functional failure over the life of usage. Meanwhile, the contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-ground rule devices. The contact resistance, together with NBTI/PBTI, cumulatively worsens the SRAM stability, and leads to severe SRAM performance degradation. Furthermore, most state-of-the-art SRAMs are designed with power-gating structures to reduce leakage currents in Standby or Sleep mode. The power switches could suffer NBTI or PBTI degradation and have large contact resistances. This paper presents a comprehensive analysis on the impacts of NBTI and PBTI on power-gated SRAM arrays with high-k metal-gate devices and the combined effects with the contact resistance on SRAM cell stability, margin, and performance. NBTI/PBTI tolerant sense amplifier structures are also discussed.

Impact of NBTI/PBTI on SRAM Stability Degradation

We investigate the impact of negative-bias temperature instability (NBTI) on the degradation of the static noise margin (SNM) and write noise margin (WNM) of a SRAM cell. This is based on the quantitative simulation of the statistical impact of NBTI on p-MOSFETs corresponding to a 45-nm low-power technology generation. Due to the increasing importance of positive-bias temperature instability (PBTI) of n-MOSFETs with the introduction of high-/v/metal gate stacks, we also explore the additional impact of PBTI on statistical SNM and WNM degradation behavior. The results indicate that NBTI-only induced SNM and WNM degradations follow different evolutionary patterns compared to the impact of simultaneous NBTI and PBTI degradation, and high distribution moment information is required for the reconstruction of noise margin distributions.

Degradation of High-$k$/Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology

The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32-nm bulk CMOS technology was studied using I- V characteristics and charge pumping measurements. The impact of stress on drain saturation current (Idsat), threshold voltage (Vt), transconductance peak (gm), and subthreshold swing (SS) is reported. For ESD stress applied on the drain, little degradation was observed until the device failed by drain-to-source filamentation. In contrast, for stress applied on the gate, positive ESD-like stress decreases Idsat and increases Vt of the nMOSFETs significantly, and the degradation increases with the effective gate oxide thickness. Different from positive bias temperature instability (PBTI) stress, the Vt shift depends on temperature rather weakly, which indicates a new dominant charge-trapping mechanism on the time scale of ESD events. In addition to the degradation of Vt and Idsat, the positive stress also caused significant damage to the Si/oxide interface in the nMOSFETs with thick gate oxide. The degradation of Idsat, Vt , gm, and SS under positive stress is more severe for devices with high-k gate compared to devices with SiON gate. It is also shown that the degradation induced by negative ESD-like stress applied on the gate is much smaller compared to positive stress. Finally, the impacts of the stress on the gate leakage current and on the the subsequent PBTI degradation kinetics are also studied.

Impact of Hf content on positive bias temperature instability reliability of HfSiON gate dielectrics

Metal–oxide–semiconductor field-effect transistors (MOSFETs) incorporating HfSiON dielectrics with different compositions have been fabricated using atomic layer deposition (ALD) and their positive bias temperature instability (PBTI) reliability has also been investigated. The experimental results indicate that the oxide trapped charge ( N ot) dominates the PBTI degradation process, and after PBTI stress the increment of oxide trapped charges (Δ N ot) is about 2–3 orders of magnitude greater than the generation of interface traps (Δ N it). Moreover, higher Hf concentration results in more pre-existing traps but slower trap creation rate. The charge pumping technique has been utilized to characterize the interfacial parameters, Δ N it, Δ N ot, and Δ D it (the generation of the density of interface trap per energy and area).

Bias Temperature Instabilities for Low-Temperature Polycrystalline Silicon Complementary Thin-Film Transistors

The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation.

Positive bias temperature instability effects of Hf-based nMOSFETs with various nitrogen and silicon profiles

Positive bias temperature instability (PBTI) effects of HfO/sub 2/-based nMOSFETs with various nitrogen profiles in HfO/sub 2/ were investigated. The nitrogen profile was modulated by an inserting Si layer (/spl sim/6/spl Aring/) into hafnium oxynitride gate dielectrics. The Si layer is used to trap nitrogen and to suppress nitrogen out-diffusion during subsequent anneals. Compared to control HfO/sub x/N/sub y/ without Si insertion, the Si-inserted HfO/sub x/N/sub y/ samples exhibited reduced PBTI degradation, especially if the Si layer was placed further from the Si interface. The improvement can be attributed to the reduction of oxide bulk trapped as well as reduced interface trapped charge generation resulting from compensation effect of inserted Si layer.