Abstract
The impact of channel flattening process, dozen digital etching (DDE), which is several dozen cyclic treatments of plasma oxidation and oxide wet etching, on device performance and reliability of Ge(1 0 0) nMOSFETs has been systematically investigated. It was found that DDE improves not only electron mobility but also Positive Bias Temperature Instability (PBTI). The PBTI degradation was found related to the pre-existing bulk traps inside gate stack instead of interfacial traps generation. DDE is considered a promising technique for constructing ultra-scaled Ge 3D channel architecture such as nanowire or nanosheet for high performance CMOS devices.
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