Abstract
Stacked nanosheet transistor (NST) has been regarded as a promising candidate to enable scaling beyond FinFET for the sub-5 nm technology node due to the superior performance. However, reliability optimization from the physical perspective, which is essential for the guideline of NST cell design, still remains unclear. In this paper, we investigate positive bias temperature instability (PBTI) degradation in the ultra-scaled n-type NST with HfO2 gate dielectric by three-dimensional-kinetic Monte Carlo method considering multiple microscopic mechanisms. Gate voltage bias and temperature dependent PBTI characteristics are presented. Furthermore, the impacts of width (Wsh) and height (Hsh), key design parameters for NST, on PBTI degradation and threshold voltage shift (ΔVth) variation are evaluated. The results show that with the larger Wsh/Hsh, PBTI becomes severer but suffers less variation and the high temperature enlarges ΔVth variation. In the case of same device perimeter, PBTI is more sensitive to the narrow Hsh side.
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