Polysilicon Gate Research Articles

A New Integration Scheme to Prevent Chemical Attack on Floating Polysilicon Gate of Non-Volatile Memory

Silicon pitting has been observed on floating gate polysilicon layer of embedded non-volatile memory(e-NVM) process due to chemical attack caused by HBr residual interacting with moisture. This paper successfully demonstrates a new integration scheme for a robust floating gate process against silicon attack for embedded stacked/split gate non-volatile memory process. Firstly, CF4 was introduced into floating gate polysilicon etch recipe to replace HBr, which has been CMOS gate polysilicon etch gas in traditional logic process due to the advantage of higher selectivity despite the disadvantage of low vaporability, for better or cleaner process control. Secondly, an additional plasma removal stripping (PRS) clean step was added before chemical removal stripping (CRS) to give better etch by-product cleaning, even though there is no photoresist and lithography involved on the poly blanket etch for the better etch by-product cleaning. This new scheme has been verified using inline optical inspection defect-scan to prove the sufficient process margin for better mass production control that came from improved manufacturing Queue-time margin (longer waiting time) between dry-etch step, CRS step, and subsequent downstream process steps. Keywords—Flash Memory, NVM, Floating Gate, HBr, Plasma Etching, Q-time, Chemical Attack, Silicon Pitting

A New Integration Scheme to Prevent Chemical Attack on Floating Polysilicon Gate of Non-Volatile Memory

—Silicon pitting has been observed on floating gate polysilicon layer of embedded non-volatile memory(e-NVM) process due to chemical attack caused by HBr residual interacting with moisture. This paper successfully demonstrates a new integration scheme for a robust floating gate process against silicon attack for embedded stacked/split gate non-volatile memory process. Firstly, CF4 was introduced into floating gate polysilicon etch recipe to replace HBr, which has been CMOS gate polysilicon etch gas in traditional logic process due to the advantage of higher selectivity despite the disadvantage of low vaporability, for better or cleaner process control. Secondly, an additional plasma removal stripping (PRS) clean step was added before chemical removal stripping (CRS) to give better etch by-product cleaning, even though there is no photoresist and lithography involved on the poly blanket etch for the better etch by-product cleaning. This new scheme has been verified using inline optical inspection defect-scan to prove the sufficient process margin for better mass production control that came from improved manufacturing Queue-time margin (longer waiting time) between dry-etch step, CRS step, and subsequent downstream process steps.

A Novel Trench IGBT With N-P-N Polysilicon Gate Structure for Low EMI Noise and High Robustness

A Novel Trench IGBT With N-P-N Polysilicon Gate Structure for Low EMI Noise and High Robustness

Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

A low-resistivity titanium silicide (TiSi2) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi2. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi2 by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi2. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 1014 cm−2. The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

Blue-light-enhanced avalanche photodiode with amulti-finger grating structure for fluorescence detection.

The responsiveness of the photodetectors is critical to the accuracy of the fluorescent fiber optical temperature sensor. However, the current gain and signal-to-noise ratio (SNR) of traditional photodiodes (PDs) is low, which makes it difficult to meet the high-precision detection requirements of the system. In response to the above problems, this paper achieves a novel, to the best of our knowledge, multi-finger grating (MFG) avalanche photodiode (APD). The device combines the polysilicon gate and the space charge region formed by P+/N-Well to detect photon signals. The conversion capability of the photodetector can be significantly enhanced by the MFG structure. The principle of the device is simulated and verified by technology-computer-aided design (TCAD). The standard grating APD (SG-APD), 2-finger grating APD (2FG-APD), 3-finger grating APD (3FG-APD), and 4-finger grating APD (4FG-APD) are fabricated based on 0.18µm CMOS process. The optoelectronic detection characteristics of these devices are analyzed by establishing an optoelectronic test platform. At 480nm, the responsivity of 2FG-APD, 3FG-APD, and 4FG-APD increases by 79.3%, 96.9%, and 70.2%, respectively, compared to SG-APD (4.021A/W). The test results indicate that 3FG-APD exhibits a strong photon response in the blue light range. The device has broad application prospects in the field of fluorescence detection.

An 800V ultra-low loss field-stop insulated gate bipolar transistor with extended polysilicon gate structure

This paper proposed a Insulated Gate Bipolar Transistor with extended polysilicon gate structure (EPG IGBT) based on P-type drift region (P-Drift), which has electron inverse and accumulation layer. It designs the gate as an extended gate structure with a Bipolar Junction Transistor (BJT), extending into the collector region, and the BJT is always blocked during the switching process. When the EPG IGBT is conducting, the Nj region has a constant positive voltage, which causes the P-Drift to form an electron inversion layer and conduct. Through TCAD simulation, the EPG IGBT maintained the same Breakdown Voltage and turn-off time, while reducing its forward voltage drop (VCE(sat) = 0.98 V) and turn-off loss (Eoff = 0.89 mJ/cm2) by 36 % and 44 %, respectively, compared with FSSJ IGBT of the same process (VCE(sat) = 1.53 V, Eoff = 1.58 mJ/cm2). In addition, the static latch-up I–V and Forward Biased Safe Operating Area (FBSOA) of the EPG IGBT have been significantly improved, providing a new approach for optimizing IGBT.

A novel 4H‐SiC accumulation mode MOSFET with ultra‐low specific on‐resistance and improved reverse recovery capability

AbstractA novel 1440‐V 4H‐SiC accumulation mode MOSFET (ACCUFET) with ultra‐low specific on‐resistance and improved reverse recovery performance is proposed in this article. As for the proposed SiC ACCUFET, the channel region can be completely depleted by the P‐type heavily doped polysilicon gate to build an electron barrier and realize a normally‐off device. And a Schottky barrier diode (SBD) is integrated below the trench gates on both sides, which brings the feasibility of realizing reverse conduction function of the proposed ACCUFET. Also, the p‐shield regions under the Schottky contact metal provide a good electric field shielding effect for the gate oxide. Compared with the conventional SiC trench MOSFET, the numerical simulation results show that the specific on‐resistance (Ron,sp) of the proposed ACCUFET is reduced by more than 64%. The high‐frequency figures‐of‐merit HFOM [Ron,sp × Cgd] and HFOM [Ron,sp × Qgd] of the proposed device are improved by 53.19% and 58.74%, respectively. The reverse recovery time (trr), and reverse recovery charge (Qrr) are reduced by 23.28% and 82.73%, respectively. In addition, the results also indicate that the proposed device has a better latch‐up immunity compared with the conventional SiC trench MOSFET. The excellent device performance and the simple manufacturing process provide a good prospect for the application of the proposed device.

Effect of time-modulation bias on polysilicon gate etching

The etching characteristics were studied via time-modulation bias (bias pulsing) by varying the pulsing parameters. The etch profiles were verified using polysilicon gate structures with dense and isolated patterns. Ion energy was defined as the peak-to-peak voltage (V pp) controlled by the RF bias power. The durations of the on period and off period (off time) of bias pulsing were adjusted by the pulse frequency and duty cycle. Profile evolution was observed in the variations in V pp and off time. Increasing the ion energy induced vertical profiles of dense patterns and the tapered profiles of isolated patterns. Extending the off time of bias pulsing induced tapered profiles of dense patterns and vertical profiles of isolated patterns. These results indicated that increasing the ion energy and pulse off time simultaneously was the direction to achieve anisotropic etch profiles for both the isolated and dense patterns.

Secondary ion mass spectrometry quantification: Do you remember when a factor of 2 was good enough?

Well, do you remember when a factor of 2 was good enough? Probably, not unless you have been around secondary ion mass spectrometry (SIMS) since the early 1960s, like one of us has been. This paper will give many references back to the early days of quantification when a local thermal equilibrium model was used to obtain the first results that were accurate to within a factor of 2, but only 60% of the time. It only worked for bulk silicate matrixes. People were not even using SIMS on semiconductors in those days. Several early references showing profiles of ion implants in Si will be referenced, but it was not until 1980 that the first paper was published that explicitly showed how to use ion implants as SIMS standards. People were using ion implants as standards before 1980, but only in limited cases, and with no formal published equations specifying how to use them. But, the samples for which ion implants were used as standards were for dilute concentrations in a single matrix, which had a uniform matrix composition with depth. The rest of the paper will show how we at Eurofins EAG Laboratories tackled the problem of quantification of both major and minor elements in nonuniform, multi-element matrices with continuously graded composition changes using point-by-point CORrected-SIMS. These include SiGe heterostructure bipolar transistors, AlGaAs vertical cavity surface emitting lasers, and B plasma-implanted poly-silicon gates.

The effect of gate geometric effect and polysilicon doping on the performance of scaled NMOS

Insufficiently high doping in polysilicon gates of metal oxide semiconductor field effect transistor (MOSFET) becomes unavoidable due to the demands for low-energy ion implantation and limited annealing conditions to achieve ultra-shallow source and drain junctions. This results in the poly-depletion effect for ultra-thin MOSFET, loss of current drive and shift in the threshold voltage. This problem gets intense when the device is further scaled down for the gate length and thickness of gate oxide. Hence, our current work focuses on the effect of gate geometrical effect and polysilicon gate doping on scaled n-channel MOSFET(NMOS) performance. The NMOS device was constructed using TCAD ATLAS tools from SILVACO software. Six different gate lengths of 0.6 μm, 0.4 μm, 0.2 μm, 60 nm, 40 nm and 20 nm were set, and the n-type doping concentration in the polysilicon gate was varied to 1× 1018, 1× 1020 and 1 × 1021 cm-3 respectively to see their effect on the NMOS I-V and C-V performances. The findings showed that as the gate length is scaled down, the drain current increases, and as the concentration of the polysilicon doping increases, the value of the threshold voltage, VTH decreases. Based on the simulation and data collected, it can be concluded that the optimum concentration of polysilicon doping that can reduce the poly-depletion effect is 1 × 1021 cm-3, and the optimum gate length that can be used to overcome the problem is 20 nm.

Investigation of Failure Mechanisms of 1200 V Rated Trench SiC MOSFETs Under Repetitive Avalanche Stress

In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance caused by thermal fatigue is observed.

(Digital Presentation) Research on Single Wafer RCA Clean in High Aspect Ratio Trenches

High aspect ratios trench are commonly used in shallow trench isolation (STI) or Gate Poly-silicon structures by dry etching of a silicon substrate. During the dry etching process, polymerization residues are produced inside the trench. These polymerization residues must be removed before the next deposition process. Watermarks might also form by poor drying after the wet cleaning process of high aspect ratio structures, which can seriously affect the next process. In this paper, we show the performance of single wafer RCA cleaning technology in high aspect ratio structures. Polymer residues can be removed by diluted HF and SC1 with megasonic technology, without the appearance of watermarks after drying. This study focuses on polymerization residues and watermarks using inline defect detection to qualify the performance of single wafer RCA clean. Yield is the final verification for proving the single wafer RCA clean.

Improving the reliability of MOS capacitor on 4H-SiC (0001) with phosphorus diffused polysilicon gate

The interface states and reliability of 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with thermal gate oxides have been researched widely. Several reports have researched the gate oxide process itself, but the effects of subsequent processes should not be ignored. In this paper, the reliability of thermal gate oxide films followed by polysilicon gate (poly-gate) process, which are widely used in MOSFET manufacture, and Al gates were compared. The poly-gate samples markedly affected the performance measured by time-zero dielectric breakdown and time-dependent dielectric breakdown methods because the phosphorus content diffused during poly-gate formatting; this was especially advantageous in reducing leakage current and improving the charge-to-breakdown (Q BD). After electronic characteristics measurements, scanning electron microscopy cross-sections were also used to analyze the breakdown mechanism. We observed an intermediate layer between the Al gate and the oxide that may cause the barrier height to be smaller than that of the poly-gate. The Al work function and polysilicon Fermi level determine the gate leakage currents and the resultant gate oxide reliability, whereas the Al2O3 gate sample has a smaller work function offset (0.7 eV) than ideal Al gate and poly-gate samples. The results imply that the reliability of the Al gate samples may be an intrinsic problem.

All Silicon Microdisplay Fabricated Utilizing 0.18 μm CMOS-IC With Monolithic Integration

A low voltage all silicon microdisplay is presented based on MOS-like gate-control all-Silicon light-emitting diode (LED) in standard 0.18 μm complementary metal oxide semiconductor (CMOS) technology. The MOS-like LED is designed under a PN alternate structure with polysilicon gate control electrode for high luminous intensity and low operating voltage. The microdisplay device is fabricated based on the LED as pixel units. The size of the proposed microdisplay device is 6.2 mm × 5.0 mm with a about 368 mW/mm2 luminous intensity at the stable operating voltage of 1.8 V.

Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications

A2RAM devices are fabricated using an adaptation of Si-nanowire process flow, including a Si-SiGe heterostructure. We present the effects of gate length, film thickness, bridge implantation conditions and the presence of LDD impacts on A2RAM memory performance. Despite the accidentally undoped polysilicon gate, we succeed in demonstrating 1T-DRAM programming and operation.

The Impact of Polysilicon Gate Doping on the Low Frequency Noise of MOS Transistors

New results are presented for the low frequency noise (LFN) characterization of N-MOS and P-MOS from a standard CMOS technology node. The impact of n[Formula: see text] and p[Formula: see text] polysilicon gate doping on the LFN for N-MOS and P-MOS devices has been investigated. The results demonstrate that the higher p[Formula: see text] poly doping of the P-MOS improves the noise performance up to a factor of six. The N-MOS device with higher n[Formula: see text] poly doping shows no significant change in the LFN level. It is interesting to note that the effective Coulomb scattering prefactor [Formula: see text] increased for both devices.

Silicon Metal–Oxide–Semiconductor Transistor with a Dependent Pocket Contact and Two-Layer Polysilicon Gate

Silicon Metal–Oxide–Semiconductor Transistor with a Dependent Pocket Contact and Two-Layer Polysilicon Gate

A novel SiC power MOSFET with integrated polySi/SiC heterojunction freewheeling diode

The adoption of intrinsic body diode of SiC MOSFETs as freewheeling diode (FWD) always induces high conduction loss and reverse recovery loss, therefore it is highly desirable to integrate a low loss FWD in SiC MOSFET. In this paper, we propose a new concept of monolithically integrating a polySi/SiC heterojunction diode (HJD) in SiC planar MOSFET (HJDMOS) without sacrificing MOSFET cell density or increasing much processing complexity. The HJD is formed between the gate polysilicon and the SiC JFET region using the same polysilicon deposition, thus the MOSFET and FWD can share the JFET and drift region in a time-multiplexing way. The SiC HJDMOS not only inactivates the body diode by offering lower turn-on voltage but also shows excellent reverse recovery characteristics because the HJD behaves like a Schottky barrier diode. Meanwhile, the gate-to-drain charge (Q gd) and gate-to-drain capacitance (C gd) of the SiC HJDMOS are significantly reduced by 8.0 times and 4.6 times in comparison with the conventional MOSFET due to the reduction of the overlapping area of gate and drain region. With optimal selection of design parameters, the integrated device maintains good MOSFET performances with forward blocking voltage of >1200 V and specific on-resistance (R on,sp) of 2.2 mΩ cm2. Therefore, the obtained figure-of-merits ( and ) of SiC HJDMOS are improved by around 7.5 times and 4.3 times, respectively. The enhanced performances suggest that SiC HJDMOS is an excellent choice for high efficiency and high frequency power electronic applications.

A novel SiC trench MOSFET with integrated Schottky barrier diode for improved reverse recovery charge and switching loss

AbstractIn this paper, a novel silicon carbide (SiC) trench metal oxide semiconductor field effect transistor (MOSFET) with improved reverse recovery charge and switching energy loss is proposed and investigated utilising ISE‐TCAD simulations. The proposed structure features an integrated Schottky barrier diode on one side‐wall of the trench below the P‐base region, and an inserted thicker oxide layer between the polysilicon gate and source metal on one side‐wall of the trench. The simulation results show that compared with Infineon's CoolSiC™ Trench MOSFET, the proposed device decreases the gate charge Qg by 29.2%, leading to significantly improved figures of merit (Ron,sp × Qg). The reverse recovery charge Qrr and peak reverse recovery current (IRRM) are reduced by 64.1% and 66.0%, respectively. Meanwhile, the total switching energy loss decreases 36.7% for the dynamic performance.

RF Performance of Devices Processed in Low-Temperature Sequential Integration

RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GHz for a gate length of 45 nm and ${V}_{\text {DD}} = -1$ V. Moreover, we demonstrate that the low- ${k}$ SiCO oxide spacer and low polysilicon gate resistance obtained with the low temperature process contribute to ${f}_{\text {max}}$ results that are better than high temperature process (above 1000°). Finally, we illustrate the crosstalk effects and the influence of the low-tier transistor gate voltage ${V}_{\text {G}}$ on the top-tier threshold voltage ${V}_{T}$ . We also show that a polysilicon ground shield integrated under the top-tier transistor substantially attenuates the intertier RF field coupling effects.