A New Integration Scheme to Prevent Chemical Attack on Floating Polysilicon Gate of Non-Volatile Memory

Abstract

—Silicon pitting has been observed on floating gate polysilicon layer of embedded non-volatile memory(e-NVM) process due to chemical attack caused by HBr residual interacting with moisture. This paper successfully demonstrates a new integration scheme for a robust floating gate process against silicon attack for embedded stacked/split gate non-volatile memory process. Firstly, CF4 was introduced into floating gate polysilicon etch recipe to replace HBr, which has been CMOS gate polysilicon etch gas in traditional logic process due to the advantage of higher selectivity despite the disadvantage of low vaporability, for better or cleaner process control. Secondly, an additional plasma removal stripping (PRS) clean step was added before chemical removal stripping (CRS) to give better etch by-product cleaning, even though there is no photoresist and lithography involved on the poly blanket etch for the better etch by-product cleaning. This new scheme has been verified using inline optical inspection defect-scan to prove the sufficient process margin for better mass production control that came from improved manufacturing Queue-time margin (longer waiting time) between dry-etch step, CRS step, and subsequent downstream process steps.