Polysilicon Gate Research Articles

A Novel Low Turn-Off Loss and Snapback-Free Reverse-Conducting SOI-LIGBT With Integrated Polysilicon Diodes

A novel reverse-conducting (RC) lateral insulated gate bipolar transistor based on the silicon-on-insulator (SOI-LIGBT) with integrated parallel/antiparallel polysilicon diodes ( $\text{D}_{F}$ and $\text{D}_{R}$ ) on the top of the anode active region is proposed and investigated by simulation. During the turn-off transient, the major part of the excess electron current flows through the parallel diode $\text{D}_{F}$ which achieves a low turn-off loss ( $E_{ \mathrm{\scriptscriptstyle OFF}}$ ). While during the forward-conducting state, the voltage across the p+-anode/n-buffer junction can rapidly increase to the junction’s built-in potential ( ${V}_{\text {bi}}$ ) at low anode current, which results in snapback immunity. Moreover, the antiparallel diode $\text{D}_{R}$ enables the proposed device to realize RC capability. Simulation results reveal that the proposed RC-LIGBT can realize superior $E_{ \mathrm{\scriptscriptstyle OFF}}$ - $V_{ \mathrm{\scriptscriptstyle ON}}$ tradeoff relationship than both the conventional LIGBT and the separated shorted-anode LIGBT (SSA-LIGBT). When $E_{ \mathrm{\scriptscriptstyle OFF}}$ is 0.44 mJ/cm2, $V_{ \mathrm{\scriptscriptstyle ON}}$ of the proposed RC-LIGBT is 1.95 V, which is 0.47 V lower than that of the SSA-LIGBT. Under ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 1.95 V, $E_{ \mathrm{\scriptscriptstyle OFF}}$ of the proposed RC-LIGBT is 0.44 mJ/cm2, which is reduced by 44.3% than that of the conventional LIGBT. Furthermore, the reverse recovery charge ( ${Q}_{\text {rr}}$ ) of the proposed device is reduced by 25.8% compared with that of the conventional one. In addition, diodes $\text{D}_{F}$ and $\text{D}_{R}$ and the thin oxide layer below can be fabricated during the implementation of the polysilicon gate. Therefore, there is no extra difficulty in the fabrication process of the proposed RC-LIGBT.

An Assessment of Step Patterned Gate Oxide Superjunction Trench MOSFET for Potential Benefits

A 600 V-class step patterned gate oxide trench (SPGOT) superjunction vertical device incorporating gate engineering is proposed in this paper. An $$n^{+}$$ polysilicon gate is segregated into three steps of varied length and oxide thickness. To improve the device performance, the gate oxide in the SPGOT structure is narrow towards the source and wide towards the drain. This modification increases the gate–source capacitance, indicating higher transconductance, and reduces gate–drain capacitance, suggesting lower switching delay. The gate length is optimized to achieve enhanced performance indicators. Electrical performance is investigated and analyzed using 2-D numerical simulations. The optimized results reveal 9.7% and 26.14% reduction in specific resistance ( $$R_{\rm on} {\cdot} A$$ ) and gate–drain charge ( $$Q_{\rm GD}\cdot A$$ ), respectively, without any reduction in breakdown voltage. The engineered gate structure further exhibits a 43% and a 33.2% improvement in switching delay and figure of merit ( $$R_{\rm on}\cdot A$$ × $$Q_{\rm GD}\cdot A$$ ), respectively, over a conventional device.

High Voltage Graphene Nanowall Trench MOS Barrier Schottky Diode Characterization for High Temperature Applications

Graphene’s superior electronic and thermal properties have gained extensive attention from research and industrial sectors to study and develop the material for various applications such as in sensors and diodes. In this paper, the characteristics and performance of carbon-based nanostructure applied on a Trench Metal Oxide Semiconductor MOS barrier Schottky (TMBS) diode were investigated for high temperature application. The structure used for this study was silicon substrate with a trench and filled trench with gate oxide and polysilicon gate. A graphene nanowall (GNW) or carbon nanowall (CNW), as a barrier layer, was grown using the plasma enhanced chemical vapor deposition (PECVD) method. The TMBS device was then tested to determine the leakage current at 60 V under various temperature settings and compared against a conventional metal-based TMBS device using TiSi2 as a Schottky barrier layer. Current-voltage (I-V) measurement data were analyzed to obtain the Schottky barrier height, ideality factor, and series resistance (Rs) values. From I-V measurement, leakage current measured at 60 V and at 423 K of the GNW-TMBS and TiSi2-TMBS diodes were 0.0685 mA and above 10 mA, respectively, indicating that the GNW-TMBS diode has high operating temperature advantages. The Schottky barrier height, ideality factor, and series resistance based on dV/dln(J) vs. J for the GNW were calculated to be 0.703 eV, 1.64, and 35 ohm respectively.

High performance selective buried double gate power MOSFET

In this letter, we propose a dual laterally aligned poly-silicon selective buried gates power MOSFET (SBGP-MOSFET). The proposed structure significantly improves the ON resistance (Ron)-breakdown voltage tradeoff, reduces gate-drain capacitance (CGD) and eliminates the formation of parasitic n–p–n transistor in comparison to the conventional vertical trench power MOSFET. The two buried gates provide a large separation between the gate and drain thus reduces the gate-drain coupling, gate-drain capacitance (Cgd) and switching losses. A two dimensional simulation study shows that the proposed SBGP-MOSFET achieves a significant reduction in ON resistance, 48.33% reduction in Qgd and ∼13% increase in the breakdown voltage in comparison to the conventional device.

Impact of Varying Strain Energy in Oxide on Random Telegraph Noise and Associated Time Constants in Silicon Nanowire pMOSFETs

Multilevel random telegraph noise in gate-all-around silicon nanowire pMOSFET shows gate voltage overdrive-dependent interstate transitions, statistical count of which indicates the existence of oxide traps with different time constants. Following the detail extraction of the capture and emission time with gate bias, both have been found to deviate from the usual trend, as predicted by the conventional Shockley–Read–Hall statistics. Two traps in the gate–oxide have been found, in which the near interface is found to respond through the altered RTN activation energy barrier by spatially varying oxide residual strain energy, whereas the farther responds under the weak influence of the oxide strain energy. On the other hand, the emission time of near interface trap has been found to follow similar strain influenced activation barrier, but the magnitude of the emission time of the farther trap shows the hole emission through the p+ polysilicon gate–oxide interfacial trap, while favored by the electrostatic field in oxide. From RTN distributions and time lag plots, interstate transitions and state suppression in RTN are explained under the framework of two-trap postulate, in order to elucidate the unusual gate bias dependence of the measured trap time constants in silicon nanowire pMOSFETs.

Quantum dots with split enhancement gate tunnel barrier control

We introduce a silicon metal-oxide-semiconductor quantum dot architecture based on a single polysilicon gate stack. The elementary structure consists of two enhancement gates separated spatially by a gap, one gate forming a reservoir and the other a quantum dot. We demonstrate that, in three devices based on two different versions of this elementary structure, a wide range of tunnel rates is attainable while maintaining single-electron occupation. A characteristic change in the slope of the charge transitions as a function of the reservoir gate voltage, attributed to screening from charges in the reservoir, is observed in all devices and is expected to play a role in the sizable tuning orthogonality of the split enhancement gate structure. The all-silicon process is expected to minimize strain gradients from electrode thermal mismatch, while the single gate layer should avoid issues related to overlayers (e.g., additional dielectric charge noise) and help improve the yield. Finally, reservoir gate control of the tunnel barrier has implications for initialization, manipulation, and readout schemes in multi-quantum dot architectures.

Silica Nano-particle Anneal Treatment and Its Effect on Chemical Mechanical Polishing

Introduction Chemical mechanical polishing is the only one technology to obtain global planarization, which is widely applied to polish silicon, copper dual damascene structure, high/low K dielectric materials, tungsten plugs, poly-silicon gates and shallow trench isolation structure. SiO2 is widely used as abrasive for its superior properties like stability, suspension property and low viscosity There are lots of studies on silica properties. However, the detailed silica surface, inner characteristic and its effect on polishing performance are still unclear. we must also explore the silica nano-particle tiny structure difference, so we designed an experiment that we anneal the colloid silica and re-dispersed it to analyze the variety of particles properties and its influences on CMP performance.

Total ionizing dose effects of <b>γ</b> and X-rays on 55 nm silicon-oxide-nitride-oxide-silicon single flash memory cell

The total ionizing dose (TID) effects on 55 nm SONOS flash cell, caused by <sup>60</sup>Co-γ ray and 10 keV X-ray radiation source, are systematically investigated in this paper. The degradation of electrical characteristics is discussed while the underlying physical mechanism is analyzed. The drift of <i>I-V</i> characteristic curve, the degradation of memory window, and the increase of stand-by current are observed after TID irradiation separately by the two radiation sources. The data retention capability is also affected by the TID irradiation. The <i>I</i>-<i>V</i><sub>g</sub> curve of the programmed single flash cell significantly drifts towards the negative direction after TID irradiation, while the negative drift of erased state is much slower. Referring to the erased state, the drift directions of <i>I</i><sub>d</sub>-<i>V</i><sub>g</sub> curves for γ- and X-ray radiation source are obviously different. The physical mechanism of irradiation damage in a 55 nm SONOS single flash cell is discussed in detail by the energy band theory and TCAD simulations. The storage charge loss in silicon nitride layer, the charge accumulation, and the generation of interface states all together lead to the degradation of threshold voltage and stand-by current after TID irradiation. Another cause for the increase of stand-by current is the positive trapped charges in the isolated oxide induced by irradiation, which leads to the generation of leakage paths. Significant dose enhancement effect of X-ray irradiation is observed in this paper. Device model of memory transistor c is established while the dose enhancement effect of X-rays is investigated by Geant 4 tool. The high-<i>Z </i>materials above the poly-silicon gate lead to the dose enhancement effect of X-rays’ irradiation, which results in the higher degradation. The density of electron-hole pairs produced by irradiation in W layer is much higher than in Cu layer. In particular, W layer is a critical factor regardless of the thickness, which can be obviously observed in the simulation.

Charge Accumulation in MOS Structures with a Polysilicon Gate under Tunnel Injection

Charge accumulation in metal—oxide—semiconductor (MOS) structures with a doped and undoped polysilicon gate with Al contacts and without them under tunnel electron injection from the gate and silicon substrate is investigated. It is shown that negative charge is accumulated near the polysilicon gate irrespective of the injection polarity, and positive charge is accumulated near the silicon substrate. Negative charge also appears near the silicon substrate at large injection charges. The results are described with the help of a numerical model, in which the formation of electron traps with the deposition of Al contacts and the generation of electron traps during the recombination of free electrons with holes captured at traps is taken into account.

Impact of nickel silicide on SiGe BiCMOS devices

Nickel silicide (NiSi) can improve the RF performance of SiGe hetero bipolar transistors (HBT) compared to cobalt silicide (Heinemann et al 2016 IEDM Tech. Dig. 51–4). In this paper, the impact of different procedures to form NiSi on HBT and MOS devices of a 0.13 μm BiCMOS cobalt silicide technology is studied. The different NiSi formations are carried out by partly or fully Ni consumption (PC, FC) for low temperature furnace and low pressure anneals. Our investigations indicate, PC results in rough silicide surfaces and substrate interfaces, whereas FC leads to smooth surfaces and interfaces associated with lower resistivities. FC nickel silicidation at 300 °C and 450 °C exhibits an excessive NiSi growth on the STI edges of n doped source drain (N+SD) regions, reducing the breakdown voltage to substrate or p well. An enhanced NiSi growth is found for all investigated silicide schemes on narrow P+SD regions along polysilicon gates. The leakage current of these structures is caused by enlarged lateral silicidation towards the gates. The enhanced lateral NiSi growth could be suppressed by partly Ni silicidation with furnace anneals at 200 °C or 230 °C.

Development of a current mirror-integrated pressure sensor using CMOS-MEMS cofabrication techniques

PurposeThis paper aims to describe the fabrication and characterization of current mirror-integrated microelectromechanical systems (MEMS)-based pressure sensor.Design/methodology/approachThe integrated pressure-sensing structure consists of three identical 100-µm long and 500-µm wide n-channel MOSFETs connected in a resistive loaded current mirror configuration. The input transistor of the mirror acts as a constant current source MOSFET and the output transistors are the stress sensing MOSFETs embedded near the fixed edge and at the center of a square silicon diaphragm to sense tensile and compressive stresses, respectively, developed under applied pressure. The current mirror circuit was fabricated using standard polysilicon gate complementary metal oxide semiconductor (CMOS) technology on the front side of the silicon wafer and the flexible pressure sensing square silicon diaphragm, with a length of 1,050 µm and width of 88 µm, was formed by bulk micromachining process using tetramethylammonium hydroxide solution on the backside of the wafer. The pressure is monitored by the acquisition of drain voltages of the pressure sensing MOSFETs placed near the fixed edge and at the center of the diaphragm.FindingsThe current mirror-integrated pressure sensor was successfully fabricated and tested using in-house developed pressure measurement system. The pressure sensitivity of the tested sensor was found to be approximately 0.3 mV/psi (or 44.6 mV/MPa) for pressure range of 0 to 100 psi. In addition, the pressure sensor was also simulated using Intellisuite MEMS Software and simulated pressure sensitivity of the sensor was found to be approximately 53.6 mV/MPa. The simulated and measured pressure sensitivities of the pressure sensor are in close agreement.Originality/valueThe work reported in this paper validates the use of MOSFETs connected in current mirror configuration for the measurement of tensile and compressive stresses developed in a silicon diaphragm under applied pressure. This current mirror readout circuitry integrated with MEMS pressure-sensing structure is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

This paper presents the impact of a short-circuit event on the gate reliability in planar SiC MOSFETs, which becomes more critical with increased junction temperature and higher bias voltages. The electrical waveforms indicate that a gate degradation mechanism takes place, showing a large gate leakage current that increases as the gate degrades more and more. A failure analysis has been performed on the degraded SiC MOSFET and then compared to the structure of a new device to identify possible defects/abnormalities. A Focused-Ion Beam cut is performed showing a number of differences in comparison to the new device: (i) cracks between the poly-silicon gate and aluminium source, (ii) metal particles near the source contact, and (iii) alterations in the top surface of the aluminium source. The defects have been correlated with the increase in gate-leakage current and drain-leakage current.

Highly Selective Silicon Dry Chemical Etch Technique for Advanced FinFET Technology

With transistor scaling in 7nm technology and beyond, sacrificial silicon materials etches (e.g. dummy poly silicon gate removal) are considered to be among the most challenging hurdle in FinFET process development. In this paper, we present a dry chemical etch technique for selective etching of single crystal, poly-crystal and amorphous silicon on various FinFET device process steps. It was demonstrated that this technique could completely remove poly silicon in vertically high aspect ratio (AR>5) FinFET gates with a large process window (over-etch budget ~200%) while achieving the lowest gate leakage current and best short channel FET yield. Proper surface preparation, queue time control and etch by-product removal strategies are discussed. The residue free etch and etch by-product sublimation mechanisms are also investigated by High Resolution Electron Microscopy (HREM) and Fourier Transform Infrared Spectroscopy (FTIR) surface analysis. This work was performed by the IBM Research at various IBM Research and Development Facilities.

Process Optimization of Deposition Conditions for Low Temperature Thin Film Insulators used in Thin Film Transistors Displays

Deposition process for thin insulator used in polysilicon gate dielectric of thin film transistors are optimized. Silane and N2O plasma are used to form SiO2 layers at temperatures below 150 oC. The deposition conditions as well as system operating parameters such as pressure, temperature, gas flow ratios, total flow rate and plasma power are also studied and their effects are discussed. The physical aspects of the yielded dielectrics such as layer thickness and uniformity are presented as well.

Effect of Reverse Body Bias on Hot Carrier Induced Degradation of n-MOSFETs

The impact of the reverse body bias (RBB) on hot carrier induced degradation of n+ polysilicon gate n-channel MOSFETs is investigated. A comparison with conventional stresses at zero body bias is given. The key role of channel initiated secondary electrons (CHISELs) under RBB stress responsible for a degradation broadly distributed along the channel is discussed. The dependence of this mechanism on channel length is highlighted and special attention is given to long channel devices suitable for analog applications. A significant threshold voltage drift is linked to a peak transconductance increase attributed to the coexistence in the channel of an undamaged region in series with a damaged one at the drain side. Peculiar impact of CHISEL damage is also visible in the degradation of drain current both in linear and saturation regions.

Monograin Defect in Polysilicon Gates

Abstract Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO2) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n+-polySi) gate. The analysis utilizes the measured gate current density JG at high oxide fields Eox in 5.4 to 12 nm thick SiO2 films between 25 and 300 °C. The leakage current measured up to 300 °C was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n +-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO2 conduction band (CB). It was observed that PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.

Breakdown and optical response of CMOS perimeter gated single‐photon avalanche diodes

The breakdown and optical response of perimeter gated single-photon avalanche diodes fabricated in a standard 0.5 μm 2-poly 3-metal CMOS process is presented. These diodes prevent premature edge breakdown through the addition of a polysilicon gate. The fabricated devices feature varying size, shape (square, octagonal, and circular), and junction types (nwell-p+ and psub-nwell) with a perimeter gate located on top of the junction. Voltage applied to the gate modulates the electric field and its effect on the breakdown voltage and optical response is discussed. Experimental results are supported by physical device simulations where applicable.

Effect of Body Bias on NBTI of p-MOSFETs

The effect of the body bias on the stability of the threshold voltage of p+ polysilicon gate p-channel MOS (pMOS) transistors stressed in the on-state is investigated. Special attention is given to pMOS transistors operating at low gate overdrive and non-zero body voltage. A mixed mode of degradation, including the usual negative bias temperature instability (NBTI) and the effect of hot-hole injection (HHI) into the gate oxide at high temperature, is reported. The relative importance of both the electric field in the gate oxide and the concentration of cold holes at the interface is pointed out for devices operating in the near threshold region. A kinetic model for NBTI/HHI is proposed.

Влияние квантования носителей в поликремниевом затворе на сдвиг порогового напряжения МДП-транзистора

Влияние квантования носителей в поликремниевом затворе на сдвиг порогового напряжения МДП-транзистора