Polysilicon Thin Film Research Articles

Thermal dependence of low-frequency noise in polysilicon thin film transistors

Thermal dependence of low frequency noise in low temperature (≤ 600 °C) polysilicon thin film transistors is studied in devices biased from weak to moderate inversion and operating in the linear mode. Drain current noise spectral density, measured in the temperature range from 260 K to 310 K, is thermally activated following the Meyer Neldel rule. Analysis of the thermal activation of noise, supported by the theory of trapping/detrapping processes of carriers into oxide traps located close to the interface, leads to the calculation of the deep state interface distribution in function of the Meyer Neldel characteristic energy.

“Hump” characteristics and edge effects in polysilicon thin film transistors

Transfer characteristics of polycrystalline silicon (polysilicon) thin film transistors (TFTs) often show a “hump” in subthreshold regime. This effect, also observed in silicon-on-insulator (SOI) transistors, can be attributed to the presence of an enhanced electrical field at edges of the channel, which is related to the specific shape of the edge and its surrounding oxide. In this paper we attempt an analysis of the hump effect in polysilicon TFTs combining electrical measurements and two dimensional numerical simulations, and considering several geometries of the channel edge. The transfer characteristics showing the hump effect are analyzed in terms of a parallel of the main (“bulk”) transistor with two parasitic transistors located at the channel edges. The main and parasitic transistors have different threshold voltages and subthreshold swings and the equivalent parallel circuit reproduces very well the experimental transfer characteristics. The effect on the hump of interface states and oxide fixed charge, localized at the edge regions, is also analyzed and it is found that a degradation of the edge interfaces can easily lead to a hump reduction, thus explaining the large variability in this effect observed for different devices and different processes.

A Simple Model of DIGBL Effect for Polysilicon Films and Polysilicon Thin-Film Transistors

Based on charge conservation assumption, analytical models of the drain-induced grain barrier lowering effect are developed for polysilicon films by 1-D Poisson's equation and for polysilicon thin-film transistors (poly-Si TFTs) by quasi-2-D Poisson's equation. It is shown that the voltage drop at the lower barrier side is less than that at the higher barrier side for both poly-Si films and poly-Si TFTs when applying a lateral bias across the grain-boundary barrier.

Low frequency noise in polysilicon thin film transistors: effect of the laser annealing of the active layer

AbstractLow‐frequency noise is studied in N‐channel polysilicon TFTs issued from two (low temperature ≤600 °C) technologies: furnace solid phase crystallized (FSPC) and laser solid phase crystallized (LSPC) TFTs. The distribution of the trap states (DOS) into the polysilicon bandgap determined for devices biased in the weak inversion is one decade lower for LSPC devices. The high range values (10–4 ≤ α ≤ 1) of the measured macroscopic noise parameter, defined according to the Hooge empirical relationship, are explained by the drain current crowding due to structural defects within the active layer. The higher values of α for the LSPC TFTs are attributed to a better structural quality of the active layer. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Effects of mechanical strain on laser crystallized polysilicon thin film transistors and ring oscillators fabricated on stainless steel foil

In this paper the influence of mechanical tensile strain on the performance of thin film transistors (TFTs), with various channel geometries, and of ring oscillators, with 3, 7, 11, 21, and 51 number of stages and device channel lengths of 1, 4, and 8 μm, fabricated on stainless steel foil substrate is investigated. TFT parameters such as field effect mobility, threshold voltage, subthreshold slope, leakage and gate current for both n-channel, and p-channel TFTs are studied at various longitudinal tensile strain levels. For strain levels from 0.0% to 0.5%, the field effect mobility of n-channel TFTs increases while that of p-channel ones decreases as the longitudinal tensile strain increases. The field effect mobility, of both n-channel and p-channel TFTs, becomes independent of longitudinal tensile strain at strain levels greater than 0.5%. Threshold voltage and subthreshold slope of p-channel TFTs increases while that of n-channel ones does not follow a specific trend. The leakage current of both type devices tends to decrease by increasing the longitudinal tensile strain. The propagation delay, per inverter stage of a ring oscillator, is investigated at different supply voltages and tensile strain levels. The propagation delay of inverters with longer device channel length (⩾4 μm) tends to decrease while that of shorter length tends to increase as the longitudinal tensile strain increases.

Forming carbon nanotube composites by directly coating forests with inorganic materials using low pressure chemical vapor deposition

Low pressure chemical vapor deposition has been used to fill carbon nanotube (CNT) forests with inorganic materials (polysilicon and silicon nitride). Forest filling proceeds by deposition around individual CNTs. As the coating thickness around each CNT increases, the free volume between adjacent nanotubes is filled and finally results in a contiguous composite film. The process maintains the forest height and alignment; however, the coating thickness around the CNTs is in general smaller at the base of the forest than it is at the top. This can cause a contiguous solid film to form at the top of the forest while the forest is only partially filled at the base. Once the top of the forest becomes filled, it prevents growth from occurring at the base. Consequently, the growth process can cap the top of the forest and leave voids between thinly coated CNTs at the base. Such composites have reduced hardness (4 GPa or less). Depositing at reduced temperatures and/or decreased precursor gas flow rates reduces the void fraction through improving the step coverage modulus. This allows one to produce thick (> 50 μm) polysilicon-CNT composite films having hardness approximately equal to that of polysilicon thin films (12.4 GPa).

High Voltage, Moderate Current Thin Film Transistor for Actuator Applications

An n-type multiple-gate laser-crystallized Poly-Silicon Thin Film Transistor (TFT) is introduced as a high voltage (Vg>30v, Vds>35v) moderate current (I=50mA) TFT structure for general purpose, matrix format actuator application on stainless steel substrate. The off-state performance of the device has been simulated and studied by the Silvaco software package and the performance of the structure has been compared with the commonly used High Voltage (HV) TFT structures.

A physical model of floating body effects in polysilicon thin film transistors

Based on a closed form of the base–emitter voltage of the parasitic bipolar transistor, a physical model of floating body effects is proposed for polysilicon thin film transistors, which takes into account the polysilicon graded pn junction and the generation rate including the Poole-Frenkel effect. Simulated results by this model are in good agreement with experimental data. It is shown that the action of a parasitic bipolar transistor should be taken into account only when the channel length is short enough due to the much smaller carrier mobility in polysilicon compared with single crystalline silicon. Whereas, the parasitic bipolar transistor gain (β) increases sharply with decreasing the channel length when the channel length is less than 5μm, which is due to the rapid increase of the base transport factor (αT).

Strength Behaviour of Polysilicon Thin Film Flexure Hinge

This work reports on strength behaviour of polysilicon thin film flexure hinge. In order to develop a microscopic modelling of thin film flexure hinge for microstructures, in situ test benches have been designed and fabricated. The experiment demonstrated that a deviation between the macroscopic theory value and experimental result. A model similar to that used for rotational stiffness in macroscopic steel is used to fit testing data for polysilicon film flexure hinge. The dynamic characteristic and fatigue behaviour of the thin film flexure hinge were also investigated. The hinge was excited by an integrated electro-thermal microactuator that could be self-heated and driven. Resonant frequency of the polysilicon flexure hinge test benches is 6.5 Hz, and the maximum operating frequency reached 1KHz. When a cyclic loading of 1μN.μm was exerted to the micromachining flexure hinge, the limit stress alternation number exceed 1.0×108. When the stress alternation number exceeded 1.0×109, the polysilicon beam of microactuator would lost its elastic character. If the micro hinge operated at high temperature (exceed 200/), the lifetime would decreased. If the working temperature were too high, the micro hinge would be burned out.

Silicon Thin-Film Solar Cells

We review the field of thin-film silicon solar cells with an active layer thickness of a few micrometers. These technologies can potentially lead to low cost through lower material costs than conventional modules, but do not suffer from some critical drawbacks of other thin-film technologies, such as limited supply of basic materials or toxicity of the components. Amorphous Si technology is the oldest and best established thin-film silicon technology. Amorphous silicon is deposited at low temperature with plasma-enhanced chemical vapor deposition (PECVD). In spite of the fundamental limitation of this material due to its disorder and metastability, the technology is now gaining industrial momentum thanks to the entry of equipment manufacturers with experience with large-area PECVD. Microcrystalline Si (also called nanocrystalline Si) is a material with crystallites in the nanometer range in an amorphous matrix, and which contains less defects than amorphous silicon. Its lower bandgap makes it particularly appropriate as active material for the bottom cell in tandem and triple junction devices. The combination of an amorphous silicon top cell and a microcrystalline bottom cell has yielded promising results, but much work is needed to implement it on large-area and to limit light-induced degradation. Finally thin-film polysilicon solar cells, with grain size in the micrometer range, has recently emerged as an alternative photovoltaic technology. The layers have a grain size ranging from 1 μm to several tens of microns, and are formed at a temperature ranging from 600 to more than 1000∘C. Solid Phase Crystallization has yielded the best results so far but there has recently been fast progress with seed layer approaches, particularly those using the aluminum-induced crystallization technique.

Efficient solar cells based on fine-grained polysilicon

Thin films of polysilicon are an attractive material to reduce the cost of photovoltaic energy. Among the different polysilicon techniques, fine-grained polysilicon deposited directly onto a foreign substrate is an interesting option, since no extra seed layer or crystallization step is needed. However, the fabrication of efficient fine-grained polysilicon solar cells is a real challenge due to the large number of defects and the small average grain size of only 0.2 µm. This paper reports on our recent progress with fine-grained polysilicon solar cells. Using a diffuse refracting top surface and a more efficient two-step hydrogenation, we obtained an efficiency of 5.0%.

Effect of the single grain boundary position on surrounding-gate polysilicon thin film transistors

In this paper, single-grain-boundary (GB)-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e., gate-all-around (GAA)) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device–circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of a single GB near the drain side has an bad effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of the threshold voltage can be reduced from 15% to 5%, with varying gate structures of the GAA polysilicon TFT.

High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization

In this work, high-performance low-temperature poly-silicon (LTPS) thin film transistors (TFTs) with double-gate (DG) structure and lateral grain growth have been demonstrated by excimer laser crystallization (ELC). Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current–voltage characteristics as compared with the conventional solid-phase crystallized (SPC) poly-Si double-gate TFTs or conventional ELC top-gate (TG) TFTs. The proposed ELC DG TFTs ( W/ L = 1.5/1.5 μm) had the field-effect-mobility exceeding 400 cm 2/V s, on/off current ratio higher than 10 8, superior short-channel characteristics and higher current drivability.

The residual stress-induced buckling of annular thin plates and its application in residual stress measurement of thin films

The buckling method is presently one of the most commonly used methods in residual stress measurement, but still suffers from the problem that an array of structures occupying a large die area is required. In this paper, the buckling characteristics of annular thin plates were investigated and a new buckling method based on annular thin plates was proposed, implemented and verified for in situ measurement of both compressive and tensile stress with only a single structure but not an array. Annular thin plates with variable inner radius were realized by the sacrificial oxide etching of circular thin plates. The critical inner radius was measured by an optical microscope and was used to predict the residual stress by eigenvalue buckling analysis of ANSYS software. To measure both tensile and compressive stress with the same structure was proved to be feasible. Further measurements of compressive stress in thin polysilicon films have been carried out by this method and have shown reasonable agreement with results by micro-rotating gauge method.

Subthreshold characteristics of polysilicon TFTs

A new analytical polysilicon thin film transistors (poly-Si TFTs) subthreshold current model is presented in this paper. The model is based on the surface potential in subthreshold regime. When assuming an exponential distribution of defect states density, surface potential calculation is derived by using the Lambert W function, which benefits from computational efficiency and is suitable for implementation in circuit simulation. In order to model the subthreshold characteristics, we have calculated the drain current and subthreshold swing. The subthreshold variation with temperature and kink effect is studied. The off-current around flat-band voltage is also calculated. The results are compared with the available experimental data and an excellent agreement has been obtained.

Low-temperature polysilicon thin film transistors on polyimide substrates for electronics on plastic

In this work we show a new low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) fabrication process on polyimide (PI) layers. The PI is spun on Si-wafer used as rigid carrier, thus overcoming difficulties in handling flexible freestanding plastic substrates, eliminating the problem of plastic shrinkage with high temperature processing and allowing the use of standard semiconductor equipment. LTPS TFTs are fabricated according to a conventional non self-aligned process, with source/drain contacts formed by deposition of a highly doped Si-layer and patterned by a selective wet-etching. Laser annealing is performed providing simultaneous dopant activation and crystallization of the active layer. The maximum process temperature is kept below 350 °C. After LTPS TFTs fabrication, the PI layer is mechanically released from the rigid carrier, which can be re-used for a new fabrication process. The devices exhibit good electrical characteristics with field effect mobility up to 50 cm 2/V s. Analysis of electrical stability and characteristics in presence of mechanical stress is also shown.

Hot-carrier stress induced degradation of SLS ELA polysilicon TFTs – Effects of gate width variation and device orientation

The DC stress induced device degradation of sequential lateral solidification (SLS) polysilicon thin film transistors (TFTs) was investigated by monitoring the threshold voltage, subthreshold slope and maximum of transconductance in the linear regime of operation. Devices with different channel widths and orientations relative to grain boundary directions were compared. It was observed that the degradation of device parameters during hot-carrier experiments was dependent on the channel width. In particular, it was found that there exist two degradation mechanisms and that one of them is width-dependent.

Impact of Preferential P-Diffusion Along the Grain Boundaries on Fine-Grained Polysilicon Solar Cells

Thin-film polysilicon solar cells are a promising low-cost alternative for bulk silicon solar cells due to their reduced material thickness. Recently, we showed that the use of an amorphous silicon/polycrystalline silicon heterojunction emitter instead of a diffused homojunction emitter led to a boost in the open-circuit voltage by 90 mV. Now, we present a full evidence that shows that this improvement is related to the absence of dopant smearing along the grain boundaries. By using scanning spreading resistance microscopy, we found an enlargement of the junction area by a factor of five in case of a homojunction. The tips of the dopant spikes represent lowly doped areas with an enhanced recombination.

Secondary cracking at grain boundaries in silicon thin films

In this article, we report irregular cleavage front transmission at grain boundaries in free-standing polysilicon thin films. When the orientations of two adjacent grains are correlated, the crack may bypass the boundary via a “tunneling” process. Similar behavior can also be achieved if the crack path curves in the grain-boundary-affected zone. Moreover, the separation of crack flanks can be aided by secondary cracking. These irregular modes of crack front behavior tend to lower the effective boundary toughness.

Growth of grains effect on boron diffusion in heavily doped LPCVD polysilicon thin films

In this study, we propose a two stream diffusion model adapted to the granular structure of polysilicon and to the effects of high-concentrations. This model takes into account temporal and thermal changes of the morphological structure of polysilicon by the grains growth during post-implantation annealing. The dopant trapping and segregation effects were combined with those of complex phenomena related to the strong concentrations such as clustering and exceeds of the solubility solid limit. This will permit to understand more exactly the significant role of the grains growth effect for the precise determination of the diffusion profiles. The adjustment of simulated profiles with the experimental SIMS profiles for short annealing times ranging between 1 and 15 minutes at the temperature of 850°C allowed the validation of this model. Grains growth and boron clustering are the major effects for the precise simulation of the diffusion profiles. The dominant mechanism of boron transfer to the grain boundaries is grains growth during which the grain boundaries collect boron by the trapping and segregation mechanism. Keywords: boron, diffusion, model, grains, grain boundaries, polysilicon. Technologies Avancees Vol. 18 2006: pp. 5-11