Abstract
The DC stress induced device degradation of sequential lateral solidification (SLS) polysilicon thin film transistors (TFTs) was investigated by monitoring the threshold voltage, subthreshold slope and maximum of transconductance in the linear regime of operation. Devices with different channel widths and orientations relative to grain boundary directions were compared. It was observed that the degradation of device parameters during hot-carrier experiments was dependent on the channel width. In particular, it was found that there exist two degradation mechanisms and that one of them is width-dependent.
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