poly-Si Layer Research Articles

Thin film Si solar cell fabricated at low temperature

Research and development of our film Si solar cells are reviewed. Our developed film polycrystalline Si (poly-Si) cells are well described by the structure of natural surface texture and enhanced absorption with a back reflector (STAR), where the active poly-Si layer is fabricated by plasma chemical vapor deposition (CVD) at low temperature. The cell with a thickness of 2.0 μm demonstrated an intrinsic efficiency of 10.7% (aperture 10.1%). By combining poly-Si cell with an a-Si cell, a stabilized efficiency of 12% has been reached for a-Si:H/poly-Si/poly-Si cell structure.

Low Temperature Poly-Si Layers Deposited by Hot Wire CVD Yielding a Mobility of 4.0 cm2V−1s−1 in Top Gate Thin Film Transistors

ABSTRACTDirect deposition of polycrystalline silicon (poly-Si) thin films by the Hot Wire CVD method has been used for the first time for the fabrication of poly-Si top gate Thin Film Transistors (TFTs). The TFTs have a high electron mobility in saturation of up to 4 cm2V−1s−1 as well as a remarkably large ON/OFF ratio of up to 6 × 105.

Fabrication and Characterization of Singly-Addressable Arrays of Polysilicon Field-Emission Cathodes.

ABSTRACTPolysilicon is a promising candidate material for field-emission microelectronics devices. It can be competitive for large-size, cost-sensitive applications such as flat-panel displays and micro electro-mechanical systems. Singly-addressable arrays of field-emission cells were fabricated in a matrix configuration using a subtractive process on Polysilicon-On-Insulator substrates. Matrix rows were fabricated as insulated polycrystalline silicon strips with sharp emission tips; and matrix columns were deposited as gold thin film electrodes with round gate openings. Ion implantation has been used to provide the required conductivity of the poly-Si layer. To reduce radius of curvature of the polysilicon tips, a sharpening oxidation process was used. The final device had polysilicon emission tips with end radii smaller than 15 nm, surrounded by gate apertures of 0.4 μm in diameter. Field emission properties of the cathodes were measured at a pressure of about 10-8 Torr, to emulate vacuum conditions available in sealed vacuum microelectronics devices. It was found that an emission current of 1 nA appears at a gate voltage of 25 V and can be increased up to 1μA at 70 V. Over this range of current, no “semiconductor” deviation from the Fowler-Nordheim equation was observed. I-V characteristics measured in cells of a 10x10 matrix, with a cell spacing of 50 μm demonstrated good uniformity and reproducibility.

Solid Phase Crystallization (SPC) Behavior of Amorphous Si Bilayer Films with Different Concentration of Oxygen: Surface vs. Interface-nucleation

ABSTRACTSolid-phase crystallization (SPC) behavior of a-Si film [a-Si(II)] in which oxygen concentration (CO) is higher at the a-Si/SiO2 interface (CO=5×1021/cm3) than at the film surface (CO=3×1020/cm3) has been investigated. The results were also compared with that of a-Si single layer [a- Si(I), 600 Å] with CO=3×1020/cm3. It has been found that the interface-nucleation was suppressed in the a-Si(II) and the surface-nucleation occurred to make a poly-Si/a-Si (300 Å/300Å) bilayer structure. Many equiaxial grains with sizes of 1∼2 [.proportional]m were formed in the surface- nucleated poly-Si layer. Compared with the results of conventional SPC poly-Si (600 Åthick) in which elliptical grains with sizes of 0.5∼1 [.proportional]m were formed by the interface (a-Si/SiO2)- nucleation, we concluded that the poly-Si/a-Si bilayer scheme is a method to improve the microstructure of SPC poly-Si film.

Trade-off and process consideration for scalable poly-Si buffered LOCOS technology

The trade-off and process consideration for the scalable usage of poly-Si buffer LOCOS (PBL) technology has been studied. By using a proper stack layer of pad-oxide/poly-Si/nitride, an available and reliable PBL process for scalable device isolation can be achieved. A dual mechanism for pit formation is proposed. As the thermal stress is too large to be sustained by the pad poly-Si, stress-induced voids are found in the poly-Si layer after field oxidation. The residual stress would considerably damage the pad oxide, eventually leading to pit formation at the mostly stressed active area while removing the pad poly-Si. On the other hand, when the stress is not sufficiently high, the pad poly-Si is just subject to stress-enhanced oxy-nitridation. A proper etching control can be employed to retain the integrity of Si substrates. As results, thicker nitride induces larger stress and thus much more easily causes pit formation. Moreover, thicker pad poly-Si can sustain larger stress, but degrade the drain-induced barrier lowering for the field isolation device. Hence, the choice of the PBL stack layer is of great importance to reduce the bird's beak encroachment and alleviate the pit formation as well as retain the gate oxide integrity and the isolation performance.

Role of Seed Crystal Layer in Two-Step-Growth Procedure for Low Temperature Growth of Polycrystalline Silicon Thin Film from SiF4 by a Remote-Type Microwave Plasma Enhanced Chemical Vapor Deposition

Role of seed crystal layer which played in low temperature growth of polycrystalline silicon (poly-Si) thin films was investigated by two-step-growth (TSG) process. The TSG involves two different deposition processes, which are called as `seed process' and `growth process'. In order to satisfy the conflicting demands such as low temperature, high rate and high quality crystal growth, the deposition conditions in the seed and growth processes were examined. As a result, it is confirmed that the seeding of high quality crystal layer is effective to improve crystallinity of growing poly-Si film, especially for the case grown at lower temperature than 300°C. In order to fully promote crystallinity, some thick and high crystallinity seed layer is needed. In addition, epitaxial-like growth on the seed layers can be realized by optimizing deposition conditions both during the seed and growth processes. When H2/SiF4 flow ratios larger than those used during the seed process were used during the growth process, lower growth temperatures were possible with maintaining a smooth interface between the seed and the grown poly-Si layers. In essence, the hydrogen mixing ratio and deposition temperature are complementary parameters, thus it was possible to reduce deposition temperatures with maintaining large crystal fraction and oriented structure, if the hydrogen mixing ratio was increased to an appropriate amount. Furthermore, in situ ellipsometry analysis indicated that, under optimal conditions, the interface between the seed and the growing film can indeed be smooth and epitaxial-like. TSG is a promising technique by which to fabricate high quality poly-Si thin films on glass substrates at low temperatures.

Suppression of boron penetration for p/sup +/ stacked poly-Si gates by using inductively coupled N2 plasma treatment

Nitridation of stacked poly-Si gates by inductively coupled N/sub 2/ plasma (ICNP) treatment has been shown to suppress boron penetration and improve gate oxide integrity. The ICNP treatments on the stacked poly-Si layers create nitrogen-rich layers not only between the stacked poly-Si layers but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. In addition, positioning of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and improvement of gate oxide reliability.

The impact of RCA treatment of glass substrates on the properties of polycrystalline silicon thin film transistors

We report on the effects of RCA leaching of glass substrates on the performance and hot-carrier reliability of n-channel and p-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). The characteristics of the TFTs on RCA-treated glass are contrasted to those of TFTs on untreated glass. It is found out that RCA treatment of the glass significantly enhances transistor’s properties. This is attributed to the formation by the RCA treatment of a silica-rich layer on the glass surface. The layer acts as a barrier for impurity diffusion from the glass to the active poly-Si layer in the TFT: this impurity diffusion is the mechanism responsible for the degradation of the TFT on bare glass.

Thin-film poly-Si solar cells on glass substrate fabricated at low temperature

The performances of thin-film poly-Si solar cells with a thickness of less than 5 μm on a glass substrate have been investigated. The cell of glass/back reflector/n-i-p type Si/ITO is well characterized by the structure of naturally surface texture and enhanced absorption with a back reflector (STAR), where the active i-type poly-Si layer was fabricated by plasma chemical vapor deposition (CVD) at low temperature. The cell with a thickness of 2.0 μm demonstrated an intrinsic efficiency of 10.7% (aperture 10.1%), an open-circuit voltage of 0.539 V and a short-current density of 25.8 mA/cm2 as independently confirmed by Japan Quality Assurance. No light-induced degradation is observed. The optical and transport properties of poly-Si cells are summarized.

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology.

Fabrication technology of ultrafine SiO2 masks and Si nanowires using oxidation of vertical sidewalls of a poly-Si layer

A fabrication technology of the vertical ultrafine SiO2 wall masks using oxidation of sidewalls of a polycrystalline silicon (poly-Si) layer and Si nanowires utilizing the SiO2 wall masks have been developed. To obtain the vertical SiO2 wall mask, an optimum electron cyclotron resonance (ECR) plasma etching and a suitable wet etching of the poly-Si layer after the sidewall oxidation has been achieved. The vertical ultrafine SiO2 wall masks 10 nm wide and 90 nm high with 33 nm in space have been successfully fabricated for the first time. The dimensions of width and space become essentially smaller than the size of an electron beam resist pattern. The height is sufficient for ECR plasma etching. Si nanowires 10 nm wide and 18 nm thick have been precisely obtained by the ECR plasma etching of the thinned silicon-on-insulator layer using the vertical ultrafine SiO2 wall masks. The fabrication technology using the vertical ultrafine SiO2 wall masks has remarkable merits of fineness, scalability, and wide applicability. It can be utilized for fabricating various designed nanostructures.

Growth and physical properties of in situ phosphorus-doped RTLPCVD polycrystalline silicon thin films

In situ phosphorus-doped (P-doped) polysilicon (poly-Si) thin films are obtained by rapid thermal low pressure chemical vapor deposition (RTLPCVD) in a single chamber RTP machine by using diluted silane (SiH 4/Ar=10%) and phosphine (PH 3=200 ppm). Deposition kinetics of poly-Si films were studied in the 600–850°C temperature range at fixed total pressure of 2 mbar and gas flow rate (100 sccm). Activation energy of 1.82 eV was calculated in the surface reaction deposition regime. Dopant activation has been obtained sequentially by RTO at 1000°C in pure O 2 atmosphere. This later process permits to both activate the phosphorus dopant and forms an ultrathin polyoxide which blocks dopant outdiffusion. Secondary ion-mass spectrometry (SIMS) analysis showed flat P-dopant profiles throughout the film thickness with a P concentration varying from 5.5×10 20 to 2.4×10 19 at/cm 3 when the deposition temperature increases in the 600–850°C range. Grazing incidence X-ray diffraction (XRD) has been used to study the structural properties of the poly-Si layers. It appeared particularly that the amorphous to crystalline temperature transition occurs at around 650°C. Finally, four-point probe measurements showed that sheet resitivities in the mΩ cm range can be routinely achieved for in situ P-doped RTLPCVD poly-Si films.

Light emitting diode structure based on Si nanocrystals formed by implantation into thermal oxide

Light emitting diodes (LED), continuously operable at room temperature, have been fabricated by Si + ion implantation into SiO 2 and subsequent annealing in order to form Si nanocrystals. A highly doped poly-Si layer was used to enhance injection into nanocrystals. Visible electroluminescence (EL) was observed from the LEDs with oxide thickness ⩽180 Å for bias voltages above 8 V. The EL decay transient was similar to stretched-exponential decays observed for photoluminescence (PL) from Si nanocrystals.

Aluminum-induced crystallization of amorphous silicon on glass substrates above and below the eutectic temperature

The achievement of high-quality continuous polycrystalline silicon (poly-Si) layers onto glass substrates by using aluminum-induced crystallization is reported. The crystallization behavior of dc sputtered amorphous silicon on glass induced by an Al interface layer has been investigated above and below the eutectic temperature of 577 °C. Secondary electron micrographs in combination with energy-dispersive x-ray microanalysis show that annealing below this temperature leads to the juxtaposed Al and Si layers exchanging places. The newly formed poly-Si layer is fully crystallized and of good crystalline quality, according to Raman spectroscopy and transmission electron microscopy investigations. At 500 °C, the time needed to crystallize a 500-nm-thick Si layer is as short as 30 min. By annealing above the eutectic temperatures, layer exchange is not as pronounced and the newly formed Al layer is found to contain a network of crystallized Si.

A new simple and reliable method to form a textured Si surface for the fabrication of a tunnel oxide film

In this work, a textured Si surface was formed with a new simple and reliable method for tunnel oxide fabrication. First, a thin poly-Si layer (12 nm thick) was deposited on Si surface and a 30-nm thick dry oxide film was then grown in O/sub 2/ ambient. This oxide film was served as a sacrificial oxide. The poly-Si film and Si substrate were both oxidized during thermal oxidization. After stripping this sacrificial oxide, a textured Si surface was obtained. Tunnel oxide grown on this textured Si surface has asymmetrical J-E characteristics, less interface states generation and better reliability (larger Q/sub bd/) as compared to those of normal oxide.

Poly-Si/SiO/sub 2/ laminated walk-off polarizer having a beam-splitting angle of more than 20

A spatial walk-off polarizer having a split angle of more than 20/spl deg/ in both the 1.3 and 1.5 /spl mu/m wavelength regions has been fabricated for the first time. The polarizer consists of alternate laminated layers of poly-Si and silica. The new polarizer makes the best use of the characteristics of crystal Si, namely high refractive index, and low absorption coefficients in the longer wavelength regions. A rather simplified fabrication process that utilizes the RF sputtering method is also proposed, in which only the oxygen-intake valve is used to control the deposition of poly-Si and silica layers from a single-crystal Si target. The fabricated polarizer has beam splitting angles as large as 22 and 21/spl deg/ at wavelengths of 1.30 and 1.55 /spl mu/m, respectively, being roughly four times larger than those of rutile or calcite.

Tem Studies of Polysilicon Emitter Bipolar Materials & Devices: Increased Interfacial Oxide Break-Up and Polysilicon Regrowth and Decreased Emitter Resistance by Fluorine Implantation

AbstractThe role of fluorine (F) in the break-up of the native oxide and the regrowth of As doped poly-Si layers on unpatterned Si wafers and on patterned regions of Si device wafers at temperatures of 900°C to 1000°C are investigated by TEM and by the fabrication of npn poly-Si emitter bipolar devices. Results for unpatterned wafers with F show i) a 950°C dopant drive-in anneal causes oxide break-up and regrowth after a time suitable for the fabrication of devices, ii) a pre-anneal, before the As implant, further enhances the break-up and regrowth and iii) there is an optimum F dose of 5×1015/cm2. Based on these results poly-Si emitter bipolar devices were fabricated using F=5×1015/cm2, a pre-anneal and a 900°C As drive-in anneal. The results establish quantitatively the relationship between the interface structures and the specific emitter resistance, i.e. with no F there is no break-up or regrowth and the emitter resistance is high (114Ωμm2) while with F there is break-up and regrowth and the emitter resistance is low (17Ωμm2).

Thin Film Poly-Si Solar Cell on Glass Substrate Fabricated at Low Temperature

ABSTRACTThe performances of thin film poly-Si solar cells with a thickness of less than 5 μm on a glass substrate have been investigated. The cell of glass / back reflector / n-i-p type Si / ITO is well characterized by the structure of naturally _surface texture and enhanced absorption with a back reflector (STAR), where the active i-type poly-Si layer was fabricated by plasma chemical vapor deposition (CVD) at low temperature. The cell with a thickness of 2.0 μm demonstrated an intrinsic efficiency of 10.7% (aperture 10.1%), the open circuit voltage of 0.539 V and the short current density of 25.8 mA/cm2 as independently confirmed by Japan Quality Assurance. The optical confinement effect explains the excellent spectral response at long wavelength for our cells through the PCID analysis. The higher sensitivity at long-wavelength of our cell appeared in quantum efficiency curves is well correlated to the result of reflectance measurement. The efficiency of 9.3% cell with a thickness of 1.5 pm was proved to be entirely stable with respect to the lightsoaking. Based on the result of various evaluation of diffusion length, it is postulated that the low temperature poly-Si prepared by plasma CVD gives a device quality of poly-Si film.

A novel polycrystalline silicon thin film transistor structure for improving hydrogenation effects

We have fabricated a new multi-channel polycrystalline silicon thin film transistor (ploy-Si TFT), of which structure may be more effectively hydrogenated than conventional multi-channel poly-Si TFTs. The new multi-channel TFT has stripe-cuts in the gate electrode so that more hydrogen radicals penetrate into the gate oxide and passivate the active poly-Si layer effectively. The electrical characteristics, such as threshold voltage and field effect mobility, are improved significantly compared with those of conventional multi-channel device after 90-min hydrogenation. Besides the improvement of the device characteristics, our experimental results show that the dominant hydrogenation mechanism in the poly-Si TFT is the diffusion through the gate oxide.

Characterization of thin-film silicon formed by high-speed zone-melting recrystallization process

We have studied the characterization of thin-film silicon formed by high-speed zone-melting recrystallization (ZMR) process. The dependence of crystal quality and solidification-front morphologies on scanning speed of melting heater was investigated by in situ observation of the molten-zone. It is found that solidification-front morphologies become unstable with quickening scanning speed and defect density increased extremely for a relatively thick poly-Si layer. On the contrary, by thinning the poly-Si layer, the solidification-front morphologies were kept stable at even higher scanning speeds and defect density was also kept low. In such ZMR films with low defect density, however, there are two types of subboundaries with and without branches. Furthermore, solar cells with simple structures were fabricated to evaluate the crystal quality of ZMR films. Charateristics of solar cells were strongly affected by the crystal quality of ZMR-Si films. Thus, it was clarified that stable solidification-front morphologies obtained by thinning the poly-Si layer and subboundaries without branches are suitable to obtain a highquality active layer. Consequently, the crystal quality of ZMR-Si films formed by high-speed ZMR process for a relatively thin poly-Si layer of 0.5 μm thickness and high scanning speed of 3.0 mm/s is comparable to that formed at a low scanning speed of 0.1 mm/s.