poly-Si Layer Research Articles

Three-dimensional atom mapping of dopants in Si nanostructures

Atom-probe tomography has successfully mapped three-dimensional (3D) dopant atom distributions in nanoscale volumes of Si subjected to various processing procedures. The 3D evolution of dopants, specifically effects such as dopant clustering and grain-boundary segregation, were analyzed in implanted polycrystalline Si gate contacts and implanted shallow junctions. A cluster of dimensions 2×7×8nm3 and containing 264 B atoms, was identified at the intersection of three poly-Si grains, verifying that annealing highly overdoped thin poly-Si layers does not facilitate uniformly doped and highly conductive gate contact layers.

Thermal stability of nitrogen in WNx barriers applied to polymetal gates

A polymetal gate needs a thin barrier layer for avoiding reactions between the metal layer and the polycrystalline silicon (poly-Si) layer. A tungsten nitride (WNx) barrier is better than a titanium nitride (TiNx) barrier from the viewpoint of thermal resistance to the wet hydrogen oxidizing process in H2O+H2 atmosphere. This oxidizing process is used to recover the integrity of the SiO2 gate oxide film of a metal-oxide-semiconductor transistor, whose electrical characteristics such as breakdown voltage are degraded by the dry etching process for patterning the gate electrode. Nitrogen in WNx barriers formed in N2+Ar using sputtering equipment moves to the surface and the interface with the poly-Si layer in the stacked structure during high-temperature device fabrication processes. As a result, the WNx layer changes into a W layer. We developed a technology for retaining nitrogen in the tungsten nitride barrier layers. The key is that at above 400°C, a WNx layer is formed on the sample when the flowing ratio of N2∕Ar gases into the sputtering chamber is above 0.4.

Fabrication of a ZnO piezoelectric micro cantilever with a high-aspect-ratio nano tip

This paper reports on a ZnO piezoelectric micro cantilever with a high-aspect-ratio (HAR) nano tip, which is proposed for a ferroelectric material based nano storage system. The system uses the interaction between the nano tip and a storage medium, and the HAR nano tip is needed to suppress undesirable effects caused by the small gap between the cantilever and the storage medium. The fabrication process for the cantilever with the HAR nano tip consists of three parts: the HAR nano tip formation, the cantilever fabrication, and the bonding/releasing process. The HAR nano tip is formed by the Si deep reactive ion etching for a long shaft and the anisotropic wet etching for a nano tip end. The cantilever is made up of 1 μm-thick LPCVD poly-Si layer and 0.2 μm-thick Si nitride layer, and has 0.5 μm-thick ZnO actuation layer. A final releasing process is followed by an anodic bonding process. The fabricated HAR nano tip has 6 μm side length, over 18 μm height, and less than 15 nm tip radius, which is built on the 85 μm-wide, 300 μm-long, and 1.2 μm-thick cantilever. The experimental results show a linear behavior with respect to input voltage of 1 to 5 V and the first resonance frequency at 17.9 kHz.

About the role of boundary conditions on compositional imaging with a scanning electron microscope

We consider the effects of different boundaries on the visibility of a specimen detail providing a compositional contrast in scanning electron microscopy, operating with backscattered electrons or secondary electrons. An object characterized by a gradual variation in composition, an As-doped region in Si, is investigated. The different boundaries in the cross-sectioned specimen correspond to the absence or presence of a poly-Si layer on top of the implanted region, deposited after the annealing treatment. It is shown that the interpretation model used for image formation is of paramount relevance for understanding the experimental results, indicating that the boundaries of the doped region are important in hindering or enhancing its visibility. The relevance of experimental parameters such as electron energy and probe dimension is also reported.

Influence of metal induced crystallization parameters on the performance of polycrystalline silicon thin film transistors

In this work, metal induced crystallization using nickel was employed to obtain polycrystalline silicon by crystallization of amorphous films for thin film transistor applications. The devices were produced through only one lithographic process with a bottom gate configuration using a new gate dielectric consisting of a multi-layer of aluminum oxide/titanium oxide produced by atomic layer deposition. The best results were obtained for TFTs with the active layer of poly-Si crystallized for 20 h at 500 °C using a nickel layer of 0.5 nm where the effective mobility is 45.5 cm 2 V −1 s −1. The threshold voltage, the on/off current ratio and the sub-threshold voltage are, respectively, 11.9 V, 5.55×10 4 and 2.49 V/dec.

Galvanic Corrosion of Miniaturized Polysilicon Structures

The fabrication and assembly of micro- and nanoscale sensors and actuators relies on chemical processing steps for the realization of mechanically freestanding devices. Early studies in microelectromechanical systems MEMS hinted at the possibility of adverse effects of processing on device performance. For example, with the immersion of polycrystalline silicon poly-Si in aqueous hydrofluoric acid HF solution, the modulus and fracture strength varied with acid concentration and exposure time. 1 Another study demonstrated morphology changes similar to stress corrosion cracking, with delamination occurring between poly-Si layers for material immersed in HF. 2 Others have noted a change in surface roughness, decrease in fracture strength, and alteration of fracture morphology for poly-Si immersed in HF for extended periods of time. 3 Some of these specimens were studied using transmission electron microscopy TEM and have demonstrated the formation of amorphous surface layers at the top and bottom of poly-Si, and with internal veins of porous poly-Si. 4 Last, an initial study demonstrated that nonuniform etching occurred preferential to the grain boundaries of poly-Si immersed in HF, even when the acid was in vapor form. 5 Many of the aforementioned studies make use of phosphorus-doped poly-Si, 2,3,5 but mechanical property variations are reported in undoped material as well. 1 The addition of an electrical bias is also

Design and fabrication of MEMS devices using the integration of MUMPs, trench-refilled molding, DRIE and bulk silicon etching processes

This work integrates multi-depth DRIE etching, trench-refilled molding, two poly-Si layers MUMPs and bulk releasing to improve the variety and performance of MEMS devices. In summary, the present fabrication process, named MOSBE II, has three merits. First, this process can monolithically fabricate and integrate poly-Si thin-film structures with different thicknesses and stiffnesses, such as the flexible spring and the stiff mirror plate. Second, multi-depth structures, such as vertical comb electrodes, are available from the DRIE processes. Third, a cavity under the micromachined device is provided by the bulk silicon etching process, so that a large out-of-plane motion is allowed. In application, an optical scanner driven by the self-aligned vertical comb actuator was demonstrated. The poly-Si micromachined components fabricated by MOSBE II can further integrate with the MUMPs devices to establish a more powerful MOEMS platform.

Carrier Transport in Polycrystalline Silicon Thin Film Solar Cells Grown on a Highly Textured Structure

Photovoltaic performance of polycrystalline silicon (poly-Si) thin film solar cells deposited by plasma enhanced chemical vapor deposition at a low temperature of ∼200°C have been investigated as a function of surface structures of textured substrates, which are needed for enhancing the light trapping effect. With increasing surface roughness of the substrate, the light trapping effect is increased, while the photovoltaic performance is decreased because the carrier transport in the poly-Si photovoltaic layer depends on the poly-Si microstructures which are significantly deteriorated by the surface texture. To quantify the effect of the surface roughness, a simple one-dimensional simulation model consisting of two regions, i.e., the initial growth region near the substrate with poor crystallinity and the postgrowth region, is proposed for the photovoltaic performance of the poly-Si thin film solar cells with different poly-Si layer thicknesses. The simulation result reveals that the carrier transport in the initial growth region more strongly depends on the surface roughness compared with that in the postgrowth region.

Fabrication of cantilever based mass sensors integrated with CMOS using direct write laserlithography on resist

A CMOS compatible direct write laser lithography technique has been developed forcantilever fabrication on pre-fabricated standard CMOS. We have developed cantileverbased sensors for mass measurements in vacuum and air. The cantilever is actuated intolateral vibration by electrostatic excitation and the resonant frequency is detected bycapacitive readout. The device is integrated on standard CMOS circuitry. In the work anew direct write laser lithography (DWL) technique is introduced. This laser lithographytechnique is based on direct laser writing on substrates coated with a resist bi-layerconsisting of poly(methyl methacrylate) (PMMA) on lift-off resist (LOR). Laser writingevaporates the PMMA, exposing the LOR. A resist solvent is used to transfer the patterndown to the substrate. Metal lift-off followed by reactive ion etching is used for patterningthe structural poly-Si layer in the CMOS. The developed laser lithography technique iscompatible with resist exposure techniques such as electron beam lithography.We demonstrate the fabrication of sub-micrometre wide suspended cantileversas well as metal lift-off with feature line widths down to approximately 500 nm.

Performance of Poly-Si TFTs Fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.

Crystal growth of polycrystalline silicon thin films for solar cells evaluated by scanning probe microscopy

We have studied the crystalline growth of photovoltaic-device-grade undoped polycrystalline Si (poly-Si) thin films produced by very high frequency (VHF) plasma enhanced chemical vapor deposition (PECVD) using a conductive scanning probe microscope (SPM) technique. Surface morphology and local current images are simultaneously measured for the poly-Si layers with a thickness, d, in the range of 0.5–5 μm. The week correlation between the topological height and the current maximum is observed for the samples with d⩾2 μm. On the other hand, the average current increases by two orders of the magnitude with increasing d from 0.5 to 3 μm. The increase in the crystalline fraction in the initial growth region just adjacent to the substrate after the deposition of the 0.5-μm-thick layer is a possible mechanism for the significant current increase.

Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon thin film transistors

This work examines the effects of grain boundaries on the performance and hot-carrier reliability of excimer-laser-annealed polycrystalline silicon thin film transistors (poly-Si TFTs) before and after NH3 plasma treatment. Self-aligned poly-Si TFTs, whose channel regions include a 150 nm thick laser-crystallized poly-Si layer with small grains and a 100 nm thick layer with large grains, are fabricated. Other TFTs, with large grains throughout their channels, are fabricated nearby for comparison. The trapping of electrons at grain boundaries in the drain junction creates strong local electric fields that boost the leakage current, cause the threshold voltage to decline as the drain bias increases, enhance the kink effect in the output characteristics, and degrade the hot-carrier reliability of devices. When static hot-carrier stress is applied to nonhydrogenated poly-Si TFTs for less than 104 s at VGS=10 V and VDS=20 V, hot holes are injected into the gate oxide at the same time trap states are created in the drain junction. The screening effect is observed when the same stress is applied to devices that have many grain boundaries in their drain junctions. NH3 plasma treatment prevents the trapping of electrons at grain boundaries. The performance of hydrogenated poly-Si TFTs improves, but the hot-carrier reliability of those TFTs with large grains in their drain junctions degrades. The hydrogenation causes a trade-off between the electrical characteristics and the hot-carrier reliability, and introduces irregular humps in the subthreshold region.

Excimer laser crystallized phosphorous-doped polycrystalline silicon

The influence of laser dehydrogenation and crystallization of phosphorous-doped amorphous silicon (a-Si:H) on structural and hydrogen bonding configurations is investigated. After each crystallization step the samples were characterized using Raman spectroscopy measurement. The results show that in the first step of crystallization, a stratified structure is created with a polycrystalline silicon (poly-Si) layer at the top of an amorphous layer. The crystalline volume fraction is not influenced by the incorporation of phosphor. According to Raman measurements the amount of hydrogen accommodated in large clusters increases with increasing doping concentration and after laser crystallization.

Enhancement of metal-induced crystallization in Ge/Si/Ni/SiO 2 layered structure

Influences of crystallinity in the precursor on metal-induced lateral crystallization of a-Si on SiO 2 have been investigated. It was found that the growth velocity during low temperature annealing (approx. 550 °C) could be enhanced by the pre-annealing treatment (300∼600 °C). This result triggered off the idea of MILC in multi-layered structure, i.e. a-Ge/a-Si/Ni-pattern/SiO 2. Utilization of this structure successfully enhanced MILC growth velocity. This is because crystal nucleation initiated in a-Ge modulated crystallinity in the precursor (a-Si). As a result, poly-Si with large grains (approx. 10 μm) was achieved in a short time annealing (<5 h). This will be a powerful tool to realize large poly-Si layers on insulating films for high efficiency solar cells and system-in-displays.

Aluminium-induced crystallisation of amorphous silicon: influence of the aluminium layer on the process

Thin polycrystalline silicon (poly-Si) layers can be formed by aluminium-induced crystallisation of amorphous silicon (a-Si). During annealing the initial glass/Al/a-Si layer structure is transformed into a glass/poly-Si/Al+Si structure. For the overall process the structure of the Al layer is very important. In this paper the effect of oxygen present during deposition of the Al-layer on process time and grain size is discussed. It was found that low oxygen flows ( f O 2 =1 sccm) during Al depositions cause a significant reduction in process time. However, the grain size of the resulting poly-Si films is not affected. Further increase of f O 2 does not result in further acceleration of the process. Instead of that the layer exchange becomes more and more incomplete and the resulting poly-Si films are discontinuous. Because of the considerable reduction in process time for samples with Al-layers deposited at f O 2 =1 sccm the annealing temperature could be lowered from 500 to 460 °C in order to obtain larger grains. The process was still completed within 90 min.

Analysis and Classification of Degradation Phenomena in Polycrystalline-Silicon Thin Film Transistors Fabricated by a Low-Temperature Process Using Emission Light Microscopy

The degradation phenomena in polycrystalline-silicon thin film transistors fabricated by a low-temperature process below 425°C (low-temperature-processed poly-Si TFTs) have been investigated. The types of degradation caused by self-heating and hot carriers have been classified, and these degradation phenomena have been investigated using emission light microscopy. Self-heating degradation is thought to originate in the breaking of Si–H bonds and regeneration of dangling bonds in the metal–oxide–semiconductor (MOS) interface and channel poly-Si layers. On the other hand, hot carrier degradation is considered to originate from the damage of the MOS interface and of the channel poly-Si layer near the drain of TFTs. When the gate stress voltage is equal to the threshold voltage, maximum degradation is induced because both the electric field near the drain in the channel and the electron density increase. Results of emission light spectra measurements confirmed the generation of high-energy carriers under this stress.

Origin of low frequency noise in polycrystalline silicon thin-film transistors

The low frequency noise in polycrystalline silicon thin-film transistors (TFTs) has its origin in both sources: (i) the Si/SiO 2 interface; and (ii) the grain boundaries present within the transistor channel. A model is developed which takes into account the fluctuations of carriers in both sources of noise. Noise is measured in two types of TFTs. In one type, the poly-Si layer has a low in-grain defect density (5×10 8 cm −2) and an average grain size of the order of 100 nm. In the other type of device the average grain size is of the order of 2500 nm while the in-grain defects density varies from 5×10 10 cm −2 to 5×10 12 cm −2. The noise analysis shows that for the first type, the Si/SiO 2 dominates while for the second type of device, the two sources of noise are present. The model also gives an estimation of the electronic parameters of the device.

Preparation of thin polycrystalline silicon films on glass by aluminium-induced crystallisation—an electron microscopy study

Polycrystalline silicon (poly-Si) films on glass were prepared by aluminium-induced crystallisation of amorphous silicon (a-Si). During an annealing step at temperatures well below the eutectic temperature of the Al/Si system ( T eu=577 °C) a glass/Al/a-Si stack is transformed into a glass/poly-Si/Al+Si stack. In this aluminium-induced layer exchange process the oxidation of the Al layer during the preparation of the initial glass/Al/a-Si stack plays an important role. Here we show that the aluminium oxide layer, which was formed during the preparation of the initial stack, is still present after the annealing step. The Al 2O 3 layer has corundum structure. The thickness of this layer is laterally inhomogeneous. The nucleation of the poly-Si layer starts at the Al/Al 2O 3 interface.

Effects of Film Interfaces on the Properties of Poly-Si Grown by The Metal-Induced Technique for Solar Cell Applications

ABSTRACTIn the metal-induced growth (MIG) process, the poly-Si layer hetero-epitaxially grows from a thin silicide layer, formed by reaction of a metal seed-layer and sputtered silicon, due to an extremely close lattice match between silicon and the metal silicide. The produced poly-Si has shown a promising device quality for photovoltaic applications. Recent results show that the interface of the silicide and poly-Si has a significant effect on the properties of the poly-Si which works as an active layer for photon absorption. In the study of the MIG process, two metals were used as a seed-layer, i.e. Ni and Co. Although CoSi2has a larger lattice mismatch with Si (1.2%) than does NiSi2(0.4%), the poly-Si growing from Co has a smoother interface between the poly-Si and silicide, while the one for the Ni seed-layer samples is rather rough. Backscattered XSEM shows that the Ni-contained phase extended into the Si layer by forming long spikes. This might cause crystal defects in the Si layer. The Auger depth profile also showed that the Ni atoms diffuse into the Si layer much more than does the Co. This kind of difference in interface structure causes the different properties of the poly-Si layer. X-ray diffraction (XRD) analysis on the Si layer showed that the Co seed-layer sample had a predominant growth orientation of (220) and the FWHM of 0.2°. The Ni seed-layer samples grew mainly in both &lt;111&gt; and &lt;220&gt; direction, with FWHM of 0.3° and 0.4°, respectively. By comparison, the poly-Si from the Co seed-layer had a higher carrier lifetime of 0.458μs compared to 0.305μs from Ni.

Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon

ABSTRACTPrecisely controlling the thickness of ultrathin silicon dioxide (SiO2) gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Advanced methods for producing ultrathin gates deposit both the gate dielectric and the polysilicon (poly-Si) gate electrode in a single cluster tool. This avoids the opportunity for adsorption of molecular airborne contamination (MAC) between deposition of the two layers, but necessitates measuring gate oxide thickness through a thick poly-Si layer.Variations in poly-Si grain size, amorphous silicon content, and roughness, make it very difficult to model the optical feedback in the visible spectral range to resolve ultrathin (10–20 Å) gate oxides with sufficient accuracy and repeatability for process control.This paper studies the optical behavior of the poly-Si/dielectric filmstack from 190 nm to 900 nm and the physical properties of the poly-Si layer. A more accurate modeling method is proposed to characterize the poly-Si and its top roughness layer using effective medium approximation (EMA) models. Using the new model, both a spectroscopic ellipsometer (SE) and a multi-angle multi-wavelength laser ellipsometer (MWLE) were employed to measure wafers with different poly-Si and gate oxide thicknesses. TEM was used to characterize the film thickness while roughness was determined using AFM. Good correlation was obtained between the TEM, AFM, and ellipsometry results. Excellent repeatability (0.04 Å 1σ on a 15 Å gate oxide for 10 days) and across the wafer uniformity (0.2 Å 1σ for a 49-point map) were also achieved when measuring gate dielectric films under the poly-Si with the MWLE.