poly-Si Gate Research Articles

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.

Submicron poly-Si gate Si field-emitter array for generation of a collimated electron beam

Reducing the emitter size in a field-emitter array is the most effective method to reduce the extraction-gate voltage for electron emission. This method results in reduction of power consumption and spot size on the screen for a field-emission display (FED) application. The transverse energy of the extracted electron at the gate hole is kept almost at the same value while the electron travels between the gate and the screen in the FED. Then, the lower extraction-gate voltage causes the lower transverse energy of the electron and the smaller spot size on the screen. By a fully self-aligned silicon process, a Si field-emitter array with a submicron poly-Si gate was fabricated for generation of a fine electron beam. This beam’s emission characteristics were examined. Without using the submicron lithography, the submicron size gate aperture was formed by reactive-ion etching, thermal oxidation, chemical-vapor deposition, and the etchback technique. The experimental results show that the electrons are emitted at the relatively low extraction-gate voltage of around 30 V and due to the reduction of the gate voltage, an emission image is observed with a relatively small spot size on the phosphor screen.

Reduction of carrier depletion in p/sup +/ polysilicon gates using laser thermal processing

A novel laser thermal processing (LTP) technique was used to fabricate p/sup +/-gated MOS capacitors with ultrathin gate oxides. It is found that the introduction of LTP prior to the gate activation anneal increases the carrier concentration at the poly-Si gate/gate oxide interface substantially, as compared to rapid thermal anneal (RTA) alone. Thus, LTP readily reduces the poly-depletion effect in p/sup +/-poly-Si gates. This is achieved without observable gate oxide degradation or boron penetration. Secondary ion mass spectrometry analyzes show that the boron concentration near the gate/gate oxide interface increases significantly after the post-LTP anneal. A possible mechanism for this increase in carrier concentration is the diffusion of boron atoms toward the gate oxide by a complex process known as explosive crystallization.

Failure analysis of 6t sram on low-voltage and high-frequency operation

Careful analysis of SRAM bit failure at high-frequency operation has been described. Using the nanoprober technique, MOS characteristics of failure bit in actual memory cells had been measured directly. It was confirmed that the drain current of a PMOS was about one order in magnitude smaller and the threshold voltage was about 1 V higher than that for normal bits. A newly developed, unique selective etching technique using hydrazine mixture showed these degradations were caused by local gate depletion, and TEM observation showed the PMOS gate poly-Si of the failure bit had a huge grain. Minimizing grain size of the gate poly-Si is found to be quite effective for improving drain current degradation and suppressing this failure mode.

46.1: Invited Paper: Interface — The Key to High‐Performance Poly‐Si TFT Fabrication

AbstractLow temperature process technologies for high‐performance polycrystalline Si (poly‐Si) thin‐film transistor (TFT) fabrication are discussed based on a key word — “interface”. Reduction of localized defects at two types of interfaces, namely grain boundary in poly‐Si film and gate SiO2/Si interface, successfully achieves high‐performance poly‐Si TFTs with average n‐channel mobility of 315 cm2V−2s−2, threshold voltage (Vth) of 0.86 V and subthreshold swing (S) of 143 mV/decade with small variations (1σ) of 30 cm2V−2s−2, 0.05 V and 6 mV/decade, respectively. This result indicates that control of “interface” is the key to the next generation high‐performance poly‐Si TFT fabrication.

P‐3: Improving Reliability of Low‐Temperature Poly‐Si TFTs by Nitrous Oxide Plasma Treatment

AbstractThe interface of poly‐Si thin film and gate oxide of poly‐Si TFTs were treated by N2O to reduce trap state density. The poly‐Si TFTs with and without treatment were characterized and compared. Electrical stress and thermal stability tests were also carried out for these TFTs. Results showed that the performance of poly‐Si TFTs with nitrous oxide treatment was improved significantly.

57.4: The Effect of the Roughness of the Glass Substrate on the Roughness of the Barrier Layer Used During Fabrication of Poly‐Si TFTs

AbstractDuring the fabrication of top gate poly‐Si TFT array for active matrix LCD applications, the glass substrate is coated with the barrier layer to prevent the diffusion of impurities from the glass to the TFT. In the present study, we have focused on the effect of the roughness of the glass substrate (fusion formed and polished) on the roughness of the barrier layer deposited on the glass substrate. The fusion formed substrates (1737 and EAGLE2000™, Corning) and the polished substrate from a competitor were coated with a barrier layer and the roughness of the barrier layer was measured by AFM. The roughness of the barrier layer deposited on the fusion formed substrates is much lower than that formed on the polished substrate. Thus roughness of the glass substrate strongly influences the roughness of the barrier layer deposited on the substrate.

Electrical properties and thermal stability of CVD HfOxNy gate dielectric with poly-Si gate electrode

High-quality, ultrathin chemical vapor deposition (CVD) hafnium oxynitride (HfOxNy) gate dielectric with poly-silicon (Si) gate electrode has been investigated for the first time. This CVD HfOxNy gate dielectric film remains amorphous after 950 /spl deg/C N/sub 2/ annealing. Compared with HfO/sub 2/ films with poly-Si gate electrode and similar equivalent oxide thickness (EOT), CVD HfOxNy shows significantly reduction in leakage-current density and boron penetration and superior thermal and electrical stability.

Properties of Polycrystalline Si1 − xGex Films Grown by Ultrahigh Vacuum CVD Using Si2 H 6 and GeH4

Polycrystalline films have been suggested as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal oxide semiconductor field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion effect than that of poly-Si gates. We investigated the formation of poly- films by using ultrahigh vacuum chemical vapor deposition CVD with and gases, and studied their physical properties as well as electrical characteristics. The deposition rate and Ge content of poly- films increased linearly with the flux of up to a critical flux, while, above this critical flux, it is slightly changed. The resistivity of poly- films decreased as the Ge content increased, and was about one-half of that of poly-Si films at a Ge content of 45%. The capacitance-voltage measurements of metal oxide semiconductor capacitor structures with gates demonstrated that the flatband voltage of the films was lower than that of poly Si films by 0.2 V. In addition, the changes of flatband voltage with the dosage of boron and the sudden decrease of accumulation capacitance in the gate structure were investigated. Leakage current levels increased slightly due to the difference in with the increase of Ge content in poly films. © 2003 The Electrochemical Society. All rights reserved.

Properties of Ultra-Thin Thermal Silicon Nitride

ABSTRACTGrowth behavior and film properties of ultra-thin Si3N4 layers formed by RTN (rapid thermal nitridation) were characterized. The self-limiting growth characteristics of the RTN process are appealing for precise thickness control in the range of 0.5–2.5nm. From SCA (surface charge analysis), the existence of negative fixed charge and electron traps in nitrides was found, in contrast to positive fixed charge and hole traps in oxides, and improvements in interface properties were seen after high temperature annealing. From annealing ambient dependences, the physical origin of the electron traps is likely N-H bonds in the nitride films. AFM (atomic force microscopy) analysis revealed that an atomically flat nitride surface is obtained by post-nitridation spike annealing, but a longer anneal leads to a rougher surface. Effectiveness of ultra-thin nitride barriers against boron penetration from a p+ poly-Si gate was also confirmed by SRA (spreading resistance analysis).

Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon

ABSTRACTPrecisely controlling the thickness of ultrathin silicon dioxide (SiO2) gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Advanced methods for producing ultrathin gates deposit both the gate dielectric and the polysilicon (poly-Si) gate electrode in a single cluster tool. This avoids the opportunity for adsorption of molecular airborne contamination (MAC) between deposition of the two layers, but necessitates measuring gate oxide thickness through a thick poly-Si layer.Variations in poly-Si grain size, amorphous silicon content, and roughness, make it very difficult to model the optical feedback in the visible spectral range to resolve ultrathin (10–20 Å) gate oxides with sufficient accuracy and repeatability for process control.This paper studies the optical behavior of the poly-Si/dielectric filmstack from 190 nm to 900 nm and the physical properties of the poly-Si layer. A more accurate modeling method is proposed to characterize the poly-Si and its top roughness layer using effective medium approximation (EMA) models. Using the new model, both a spectroscopic ellipsometer (SE) and a multi-angle multi-wavelength laser ellipsometer (MWLE) were employed to measure wafers with different poly-Si and gate oxide thicknesses. TEM was used to characterize the film thickness while roughness was determined using AFM. Good correlation was obtained between the TEM, AFM, and ellipsometry results. Excellent repeatability (0.04 Å 1σ on a 15 Å gate oxide for 10 days) and across the wafer uniformity (0.2 Å 1σ for a 49-point map) were also achieved when measuring gate dielectric films under the poly-Si with the MWLE.

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

Study of titanium silicide formation using spike anneal for integrated chip manufacturing

The use of spike anneal in titanium salicide process was studied. The area dependence of C49-to-C54 TiSi2 phase transformation was reduced for deep submicron poly-Si gate by having spike anneal during [rapid thermal annealing (RTA)] RTA1 without the use of preamorphizing implant or implant through metal. It is believed that the spike anneal during RTA1 resulted in varying amounts of C54–TiSi2, which then acts as nuclesus that grows during RTA2. Results showed that the spike anneal in RTA1 did not increase the gate to source/drain leakage current for the spike anneal temperature investigated at less than 900 °C. Results, also, show that a one-step RTA Salicide process is possible for larger linewidth devices using spike anneal.

Scalability of MOCVD-deposited Hafnium Oxide

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

Imaging breakdown spots in SiO/sub 2/ films and MOS devices with a conductive atomic force microscope

Conductive atomic force microscopy (C-AFM) was used to study the dielectric breakdown of SiO/sub 2/ layers at a nanometric scale. First, bare oxide regions were stressed and broken down using the tip as the metal electrode of a MOS structure. The results show that the initial breakdown is electrically propagated to neighbor regions, affecting their dielectric strength. Moreover, the area affected by the initial breakdown depends on the breakdown hardness. In particular, it is shown that this area is smaller when the current through the structure is limited during the experiments. The effect of the current limitation is analyzed in detail. Based on the results, a qualitative picture of the breakdown process is presented, which accounts for this effect. Finally, for the first time, the breakdown spots in standard MOS devices (with poly-Si gate) are electrically imaged with C-AFM. The areas of the observed spots are in agreement with those obtained on bare oxides.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.

Improving the yield of deep submicron CMOS processes by controlling the grain size of poly-Si gate through post deposition rapid thermal anneal

The morphology of gate poly-Si was found to be critical for achieving fully functional 4-Mb SRAM dies with 0.18-/spl mu/m complementary metal-oxide-semiconductor (CMOS) process. Although the functionality of 4-Mb SRAM had been achieved with as-deposited poly-Si gate, it is highly likely that the surface roughness of the as-deposited poly-Si is a major concern for sub-0.18-/spl mu/m technology. In this report, it is shown that the small-size grains, achieved by recrystallizing as-deposited amorphous Si via rapid thermal anneal prior to gate patterning, is very effective in reducing the number of failing bits of 4-Mb SRAM dies. The conventional deposition process for gate poly-Si can therefore be adopted for fabricating sub-0.18-/spl mu/m CMOS integrated circuits.

Quantum-Mechanical Simulation of Counter Doped Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Single Work Function Metal Gate

The quantum-mechanical effects in counter doped n-channel metal–oxide–silicon field-effect transistors (MOSFETs) for metal gate complementary metal–oxide–silicon (CMOS) have been simulated using self-consistent calculations. The energy levels and fractional occupation of subbands, gate tunneling current and channel mobility in such metal gate MOSFETs have been investigated, comparing with those in n+-poly Si gate MOSFETs. The energy levels and fractional occupation for metal gate MOSFETs are fairly different from those for poly Si gate MOSFETs since the accumulation and inversion layers are formed on the respective surfaces by positive gate voltages. The tunneling current in metal gate MOSFETs is smaller than that in poly Si gate MOSFETs. In particular, at the gate voltages below 1 V, the current density is reduced by one order or above of magnitude. Moreover, the mobility in metal gate MOSFETs with lightly counter doped channel becomes much larger than that in poly Si gate MOSFETs because of the large suppression of ionized impurity scattering and surface roughness scattering.

Atomic-layer-deposited silicon-nitride/SiO 2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (∼2 monolayers) silicon nitride layer has been deposited on thermally grown SiO 2 by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness ( T eq=2.2 nm) efficiently reduce the boron diffusion from p + poly-Si gate without the pile up of nitrogen atoms at the SiO 2/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO 2 especially in the thin (<0.5 nm) thickness region. An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO 2 stack gate dielectrics compared with those of conventional SiO 2 dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO 2 and SiO 2/Si-substrate interfaces for the SiO 2 gate dielectrics and only near the SiO 2/Si-substrate interface for the stack gate dielectrics. Employing annealing in NH 3 at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO 2, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH 3 annealing. Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.

Independence of the Soft Breakdown Phenomenon from the Gate Material: Soft- vs. Hard-Gate Capacitors

The effect of the gate material on soft breakdown is studied by using Hg instead of poly-Si as gate material. It is demonstrated that soft breakdown occurs also in Hg-gate capacitors with a probability that exhibits the same dependence on the oxide thickness and the stress voltage as observed in poly-Si gate capacitors. These results indicate that soft breakdown is a phenomenon independent of the gate material, i.e., influenced more by the details of the energy discharge in the conduction spot at the moment of breakdown than by the details of charge injection and defect accumulation in the oxide. © 2002 The Electrochemical Society. All rights reserved.