Submicron poly-Si gate Si field-emitter array for generation of a collimated electron beam

Abstract

Reducing the emitter size in a field-emitter array is the most effective method to reduce the extraction-gate voltage for electron emission. This method results in reduction of power consumption and spot size on the screen for a field-emission display (FED) application. The transverse energy of the extracted electron at the gate hole is kept almost at the same value while the electron travels between the gate and the screen in the FED. Then, the lower extraction-gate voltage causes the lower transverse energy of the electron and the smaller spot size on the screen. By a fully self-aligned silicon process, a Si field-emitter array with a submicron poly-Si gate was fabricated for generation of a fine electron beam. This beam’s emission characteristics were examined. Without using the submicron lithography, the submicron size gate aperture was formed by reactive-ion etching, thermal oxidation, chemical-vapor deposition, and the etchback technique. The experimental results show that the electrons are emitted at the relatively low extraction-gate voltage of around 30 V and due to the reduction of the gate voltage, an emission image is observed with a relatively small spot size on the phosphor screen.