Plastic Surface Mount Research Articles

CMOS Single-Chip Electronic Compass With Microcontroller

We present a CMOS single-chip electronic compass sensor including the complete digital signal processing for accurate heading calculation. The device's analog part consists of Hall- based three-axis magnetic field transducer with integrated magnetic concentrator that operates as a passive magnetic amplifier. The analog amplification chain features a gain of up to 20 000. A true-12-bit extended counting ADC converts the amplified magnetic field signals into the digital domain, where a 16-bit microcontroller calculates the heading information and outputs it via an SPI interface. The compass sensor is realized in 0.35 mum low-voltage CMOS technology plus a simple batch processing step for deposition of a metal layer. The compact die size of 2.3 mm times 2.8 mm allows for packaging into a standard 4 mm times 5 mm times 1 mm surface-mount plastic package. The heading resolution is better than 0.5deg, and the accuracy better than plusmn2deg.

Vapor Pressure and Residual Stress Effects on Mixed Mode Toughness of an Adhesive Film

Temperature- and moisture- induced delamination leading to popcorn package cracking is a major package reliability issue for surface-mount plastic encapsulated microcircuits (PEM). Crack propagation along one of the interfaces of a ductile adhesive joining two elastic substrates is modeled to study interface delamination and toughness of PEMs. The polymeric adhesive is stressed by remote loading and residual stress. Along the crack front, the film-substrate interface is modeled by a strip of cells that incorporates vapor pressure effects on void growth and coalescence through a Gurson porous material relation. Results show that under high levels of vapor pressure, increasing film thickness will produce smaller enhancement on the steady-state fracture resistance of the interface, also referred to as the joint toughness. Across all mode mixity levels, vapor pressure effects dominate over residual stress. The adverse effects of vapor pressure are greatest in highly porous adhesives subjected to a strong mode II component. The latter is representative of the likely state of loading in IC packages since residual stress, resulting from the film-substrate thermal mismatch, induces a predominantly mode II component.

Vapor pressure and residual stress effects on failure of an adhesive film

Surface-mount plastic encapsulated microcircuits (PEM) are susceptible to temperature- and moisture-induced failures during reflow soldering. Adhesive failures in PEMs are studied using a model problem of a ductile adhesive joining two elastic substrates. The polymeric adhesive contains a centerline crack. The adhesive film is stressed by remote loading and residual stresses. Voids in the adhesive are pressurized by rapidly expanding water vapor. The computational study addresses three competing failure mechanisms: (i) extended contiguous damage zone emanating from the crack; (ii) multiple damage zones forming at distances of several film thicknesses ahead of the crack; and (iii) extensive damage developing along film–substrate interfaces. The second failure mechanism is found in low porosity adhesives, while the first is dominant in high porosity adhesives. The first is also the likely failure mode when voids in the adhesive are subjected to high vapor pressure. The third damage mechanism is operative in low porosity adhesives subjected to high residual stress. In general, both residual stress and vapor pressure exert pronounced effects on failure modes. Vapor pressure, in particular, accelerates voiding activity and growth of the damage zone offering insights into the catastrophic nature of popcorn cracking.

Ultra-Wideband Radar Sensors for Short-Range Vehicular Applications

The recent approval granted by the Federal Communications Commission (FCC) for the use of ultra-wideband signals for vehicular radar applications has provided a gateway for the introduction of these sensors in the commercial arena as early as 2004. However, the rules governing the allowable spectral occupancy create significant constraints on the sensors' operation. This is further complicated by the variety of applications that these sensors are being required to fulfill. A review of the motivation for the development of these sensors is followed by a discussion of the consequent implications for waveform design and limitations on system architecture. Other practical considerations such as available semiconductor technology, packaging, and assembly techniques are reviewed, and results are presented for conventional surface-mount plastic packages illustrating their usefulness in the greater than 20-GHz frequency range. Suitable antenna technology for wide-band transmission is presented that is compliant with the specific restrictions stipulated in the FCC ruling. Finally, all of these considerations are combined with the presentation of a compatible integrated-circuit-based transceiver architecture. Measured results are presented for several critical circuit components including a +12-dBm driver amplifier for the transmitter, an RF pulse generator that can produce sub-1-ns pulses at a carrier frequency of 24 GHz, and a single-chip homodyne in-phase/quadrature down-conversion receiver that has a cascaded noise figure of less than 7 dB. All circuit components are fabricated in SiGe.

Vapor Pressure Assisted Void Growth and Cracking of Polymeric Films and Interfaces

Pores and cavities form at filler particle-polymer matrix interfaces, at polymer film-silicon substrate interfaces as well as in molding compounds of IC packages. Moisture diffuses to these voids. During reflow soldering, surface mount plastic encapsulated devices are exposed to temperatures between 210 to 260°C. At these temperatures, the condensed moisture vaporizes. The rapidly expanding water vapor can create internal pressures within the voids that reach 3–6 MPa. These levels are comparable to the yield strengths of epoxy molding compounds and epoxy adhesives, whose glass transition temperatures T g range between 150 to 300°C. Under the combined action of thermal stress and high vapor pressure (relative to the yield strength at T g), both pre-existing and newly nucleated voids grow rapidly and coalesce. In extreme situations, vapor pressure alone could drive voids to grow and coalesce unstably causing film rupture, film-substrate interface delamination and cracking of the plastic package. Vapor pressure effects on void growth have been incorporated into Gurson's porous material model and a cohesive law. Crack growth resistance-curve calculations using these models show that high vapor pressure combined with high porosity bring about severe reduction in the fracture toughness. In some cases, high vapor pressure accelerates void growth and coalescence resulting in brittle-like interface delamination. Vapor pressure also contributes a strong tensile mode component to an otherwise shear dominated interface loading. An example of vapor pressure related IC package failure, known as “popcorn” cracking, is discussed.

Reliability of new packaging concepts

Today, most of the microelectronics packaging needs are met by semiconductor devices in plastic surface mount (SM) packages. Microelectronics packaging of the future will be either bare chip or chip size/scale packaging (CSP). Of the 45 billion SM packaged ICs to be manufactured in 2000, CSPs will be a small 3.4% but growing at 62% (compound annual growth rate). The use of direct bonded chip-on-board and flip chip (FC) technology for custom solutions may not match the growth of CSPs. The popcorn problem of existing plastic packages has been solved in many ways including the use of hydrophobic composite encapsulants as the best solution and thorough bake-out and storage as the long-standing practical solution. The popcorn problem which was more severe with the smaller and thinner encapsulations of CSPs is also solved with modern hydrophobic materials and new non-paddle package designs. Further, there is good evidence that reliability is not impaired even by delaminations in the bulk of the encapsulations – small delaminations being an inevitable consequence of stress relaxation following transfer moulding. CSP and FC bump joint reliability is safeguarded both by good soldering practice and by effective underfill. High reliabilities are achievable with the range of new packages built from modern materials, with random failure rates down to 10 failure units, infant mortalities controlled to low levels by six sigma manufacturing processes and wearout lifetimes exceeding 100 years even in tropical operation.

A simplified modeling technique for finite element thermal analysis of a plastic SOIC package

The purpose of this paper is to introduce an approximate analysis method which is incorporated with an ANSYS finite element program for thermal finite element analysis of a surface mount plastic package mounted on a PC board. A numerical example is given in the paper to demonstrate the application of this technique, and the numerical prediction agrees well with the experimental results. This proposed technique can be applied to solve other thermal problems such as the analysis of any surface mount or through hole type of plastic package mounted on a PC board or can be used for determining junction temperatures of multiple power components mounted on a board.

A novel high performance adhesion enhancing Zn-Cr leadframe coating for popcorn prevention

A novel adhesion enhancing Zn-Cr (A2) leadframe coating has been reported to be a highly effective solution for popcorn prevention in plastic surface mount packages. In this paper, we report our recent understanding of the adhesion and degradation mechanisms of such a coating system. TEM and TOF-SIMS were employed to study the structure of A2-coating and the molding compound/leadframe (MC/LF) interface. The A2-coating was found to be a partially thin, crystalline layer comprised of a continuous interfacial layer and a network of whiskers. Zn silicate compound, ZnO and Cr oxide(s) were identified as possible phases present in the A2-coating. The adhesion enhancing and degradation mechanisms of the A2-coating were investigated by lead pull test to study the influence of temperature cycling, pressure cooker testing, moisture preconditioning, and leadframe oxidation. The adhesion data showed that the A2-enhanced MC/Cu LF interface is not susceptible to thermomechanical stress and moisture degradation. The wetting of the molding compound coupled with mechanical interlocking mechanism offered by the whiskers are believed to be key contributing factors of adhesion enhancement. Degradation of the A2-enhanced MC/Cu LF adhesion was observed after 100 min exposure at 300/spl deg/C by Cu oxide formation from Cu outward diffusion through the A2-layer and was validated by AES analysis operated in the depth profiling mode. Lead pull test specimens were cleaved to have access to the MC/Cu LF interface for RBS analysis to identify the locus of failure.

Time-domain characterization of packaging effects via segmentation technique

The analysis of a monolithic microwave integrated circuit (MMIC) placed in a surface-mount plastic package is presented. Critical issues such as poor grounding conditions and crosstalk are addressed and discussed. The significance of a full-wave characterization of the component is shown. Results are validated with data available in the literature showing good agreement. A segmentation approach is also proposed to efficiently analyze the problem. The package effects are extracted and can be combined with MMIC parameters at the design stage to predict the performance of the packaged circuit.

A circuit topology for microwave modeling of plastic surface mount packages

A circuit topology is described for modeling a class of plastic surface mount packages. The model consists of three pieces each of which is circuit modeled based on an electromagnetic simulation. The resulting parts of the model can then be interconnected with each other and with the model of the monolithic microwave/millimeter wave integrated circuit (MMIC) to be packaged. Various interconnections and grounding schemes can be investigated without resorting to further electromagnetic simulation. The circuit model topology is verified by circuit simulating two simple packaged test circuits and comparing the results to a full electromagnetic simulation. The resulting S parameters are in good agreement over a wide range of frequencies and for a variety of grounding configurations.

Silicon MOSFET distributed amplifier

The first reported integrated silicon MOSFET distributed amplifier is presented. A three stage distributed amplifier was fabricated on a standard 0.8 µm silicon CMOS foundry process and packaged in a SSO-24 plastic surface mount package. The required inductance needed for distributed amplification is realised by the parasitic inductance of the bond wires and lead frame inductance inside the plastic surface mount package. The distributed amplifier has a unity gain cutoff frequency of 4.7 GHz, a gain of 5 dB and an input referred third order intercept point of +15 dBm.

A 1.9-GHz GaAs chip set for the personal handyphone system

The Japanese Personal Handyphone System (PHS) is representative of the latest generation of digital portable communications systems currently being deployed. Enabling technologies for these systems include high performance Radio Frequency Integrated Circuit (RFIC) chip sets. These chip sets allow all the RF transceiver functions to be included in low cost surface mount plastic packages. With the addition of filters and bypassing capacitors, the RF portion of the phone shares the same printed circuit board (PCB) as the DSP, CODEC, and logic ICs. The availability of such highly integrated 1.9-GHz RFICs requires the solution of many complex design, manufacturing, and test problems. This paper explains the critical issues relating to the air interface of the PHS system and how it affects the RFIC design. The chip partition, design, and performance of each subfunction is discussed relative to the requirements imposed by the air interface. The result is a highly integrated, cost effective solution that occupies the minimum board area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

C-mode acoustic microscopy applied to integrated circuit package inspection

A C-mode acoustic microscope, or C-AM, is hybrid of a conventional C-scan recorder and the Stanford scanning acoustic microscope (SAM). C-AM is a reflection acoustic technique with precision scanning for microscopic inspection, sophisticated signal analysis and display and a broad-band acoustic transducer with a small numerical aperture for sub-surface imaging. The technique offers significant advantages for the nondestructive inspection of integrated circuit (IC) packages. C-AM provides 3-D information on structures and defects within the IC package. Phase analysis of the echo signal helps in the identification of delaminations and package cracks. The nondestructive nature of C-AM inspection and the sensitivity of the technique to important package defects facilitate the study of the moisture sensitivity problem in surface mount plastic packaging.

Failure analysis of multilevel metallized lsi using optical beam induced current

In order to analyse failures caused in multilevel metallized LSI devices. we developed the OBIC (optical beam induced current) observation technique using an infrared laser incident upon a backside of the chip which appears from a plastic package by being lapped and polished. We analysed the electrical rejects in the reliability stressing of surface mount plastic packages with this technique. The latch-up phenomenon in 4Mbit dynamic RAM with retrograded-well fabricated by a high energy (MeV) ion-implantation was also examined. The high latch-up immunity of the device with retrograded-well is confirmed by this analysis.

Moisture Induced Failure in Plastic Surface Mount Packages

There is a reliability concern in the larger plastic surface mounting packages which can exhibit cracks from internal stresses during soldering. A lot of ad hoc information has been given to users of such packages about the origins of the problem and its alleviation. The phenomenon is the result of a combination of moisture absorbed in the plastic and the thermal stresses caused by the different expansions of the metal leadframe and the plastic. The work reported here gives quantitative data regarding the amount of moisture absorption critical to cracking, the range of baking procedures available to reduce this moisture below the critical level, and the acceptable floor life after baking for a wide range of storage temperatures and humidities.

Mechanism of package cracking in plastic encapsulated surface mount package during reflow soldering and corrective action : Kunihiko Nishi, Ichiro Anjoh, Masatugu Ogata, Makoto Kitano and Tohru Yoshida. Proc. 18th Symp. Reliab. Maintainab. (Condensed Version), 29 (June 1988)

Mechanism of package cracking in plastic encapsulated surface mount package during reflow soldering and corrective action : Kunihiko Nishi, Ichiro Anjoh, Masatugu Ogata, Makoto Kitano and Tohru Yoshida. Proc. 18th Symp. Reliab. Maintainab. (Condensed Version), 29 (June 1988)

Moisture induced package cracking in plastic encapsulated surface mount components during solder reflow process : R. Lin, E. Blackshear and P. Serisky. Proc. IEEE/IRPS, 83 (1988)

Moisture induced package cracking in plastic encapsulated surface mount components during solder reflow process : R. Lin, E. Blackshear and P. Serisky. Proc. IEEE/IRPS, 83 (1988)

Study of soldering heat test method for plastic encapsulated surface mount packages : Masaki Tanaka, Masanori Sakimoto, Hideaki Konishi, Kunihiko Nishi, Kenichi Ohtsuka and Tohru Yoshida. Proc. 18th Symp. Reliab. Maintainab. (Condensed Version), 27 (1988)

Study of soldering heat test method for plastic encapsulated surface mount packages : Masaki Tanaka, Masanori Sakimoto, Hideaki Konishi, Kunihiko Nishi, Kenichi Ohtsuka and Tohru Yoshida. Proc. 18th Symp. Reliab. Maintainab. (Condensed Version), 27 (1988)

Surface-mount plastic packages-an assessment of their thermal performance

Thermal characteristics of surface mount (SM) plastic packages such as small-outline integrated circuit (SOIC) packages, plastic leaded chip carriers (PLCCs), and fine pitch plastic leaded chip carriers (FPPLCCs) (also known as PQFP, i.e. plastic quad flat pack) used in IC packaging are described. Experimental data are reported on single-component packages in free-air, forced-air, and liquid-immersion cooling environments. Parameters of a model to help a system thermal designer to best utilize the single-component thermal data are discussed. The influence of both the package variables (such as leadframe design, chip size, and heat spreader) and user variables (such as printed-circuit-board material, package density, and cooling mode) on the thermal performance of these packages is assessed. Opportunities to enhance the thermal performance of SM plastic packages are identified and their prospects assessed. >

Thermal Characteristics of Plastic Small Outline Transistor (SOT) Packages

Surface mount plastic packages, including small outline transistor (SOT), small outline integrated circuit (SOIC), and plastic leaded chip carrier (PLCC), are projected to be the next generation replacement for plastic dual in-line packages (DIP's). Relative to DIP's, surface mount packages are small in size and allow higher package density on a hoard, leading to higher electrical speed for system applications. However, their small size and high density mounting in close proximity to each other make thermal management more difficult. Thermal characteristics of one class of plastic surface mount packages, namely, small outline transistor 23 and 89 packages will be addressed. The most striking feature of these packages is their small size, meaning the effective package diameter is on the same order of magnitude as the board thickness. Junction to ambient thermal resistance of these packages is less sensitive to package parameters, such as thermal conductivity of leadframe, molding compound, die bond, and chip size, than to variations in local printed circuit (PC) board temperature rise. About 80 percent of the surface mount package heat flows into the board at modest board temperatures, making the local mounting environment the greatest influence on thermal resistance. Experimental thermal resistance data for single component plastic SOT-23 and SOT-89 packages are reported. Both electrical parametric and infrared (IR) techniques were used to measure these quantities. The most noteworthy observation is that the external thermal resistance is about 2/3 of the total thermal resistance and thus controls the package's thermal behavior. The effect of density of mounting on thermal resistance of the packages is measured by IR imaging experiments. Package pitch, relative orientation of neighboring packages, and one-sided versus double-sided mountings are parameters that were varied in these experiments.