Reliability of new packaging concepts

Abstract

Today, most of the microelectronics packaging needs are met by semiconductor devices in plastic surface mount (SM) packages. Microelectronics packaging of the future will be either bare chip or chip size/scale packaging (CSP). Of the 45 billion SM packaged ICs to be manufactured in 2000, CSPs will be a small 3.4% but growing at 62% (compound annual growth rate). The use of direct bonded chip-on-board and flip chip (FC) technology for custom solutions may not match the growth of CSPs. The popcorn problem of existing plastic packages has been solved in many ways including the use of hydrophobic composite encapsulants as the best solution and thorough bake-out and storage as the long-standing practical solution. The popcorn problem which was more severe with the smaller and thinner encapsulations of CSPs is also solved with modern hydrophobic materials and new non-paddle package designs. Further, there is good evidence that reliability is not impaired even by delaminations in the bulk of the encapsulations – small delaminations being an inevitable consequence of stress relaxation following transfer moulding. CSP and FC bump joint reliability is safeguarded both by good soldering practice and by effective underfill. High reliabilities are achievable with the range of new packages built from modern materials, with random failure rates down to 10 failure units, infant mortalities controlled to low levels by six sigma manufacturing processes and wearout lifetimes exceeding 100 years even in tropical operation.