Plasma Etching Research Articles

High-density integration of uniform sub-22 nm silicon nanowires for transparent thin film transistors on glass

Ultrathin catalytical silicon nanowires (SiNWs), grown as orderly arrays upon glass substrates, are ideal 1D channels for the construction of high-performance field effect transistors for low-power and high aperture/transparency electronics. In this work, a rather uniform growth integration of high-density ultrathin SiNWs has been accomplished directly on glass substrate at 290 °C, via an in-plane solid–liquid-solid mechanism. The indium (In) catalyst thickness deposited on the dense guiding terrace steps was identified as a key parameter to suppress the size dispersion of the In droplets, and thus enable a uniform growth of ultrathin SiNWs with diameters down to DNW=21.8 ± 1.8 nm, a close-to-unity guided growth rate and an excellent transparency > 90 % in spectrum ranging from 350 nm to 950 nm. Based on a convenient dry plasma etching and low-temperature passivation procedure, high-performance SiNW transistors have been successfully fabricated upon a dense array of parallel SiNWs as channels with a narrow NW-to-NW spacing of 100 nm. A high current ratio Ion/Ioff > 107, a low off-state current down to 0.1 pA, a steep subthreshold swing of SS∼120 mV dec-1 and excellent positive and negative bias stabilities have been demonstrated, as well as SiNW-based inverter logics that achieve a gain of 14.6 V/V under a drive voltage of 2.25 V. These results highlight the potential of catalytic SiNWs to serve as advantageous 1D channels for large-area display or transparent electronics.

Focused microstructure analysis and fabrication for monolithic integration with high-speed MUTC photodiode

Back-incidence high-speed photodiodes with small mesa diameter use back-integrated microstructures, which utilize the convergence and high transmittance function of the microstructures on the light beam to compensate for the incident light alignment deviation and improve the optical coupling efficiency. Two kinds of microstructures integrated with the modified uni-traveling-carrier photodiode (MUTC-PD), microlens and two-dimensional concentric annular convergence grating, are designed theoretically and compared by simulation. It is found that the microlens have better optical performance when integrated. InP microlenses meeting the requirements were fabricated using the photoresist hot melt method and inductively coupled plasma (ICP) etching. Testing revealed that the microlens could reduce the incident light spot size to one-third of its original size. By optimizing the thickness and doping concentration of the PD layer structure, and prepared a high-speed MUTC-PD with monolithic integrated InP microlens, with a mesa diameter of 18 μm. The measured 3 dB bandwidth of the integrated chip is 43 GHz. Experimental results using incident light fiber movement showed that the responsivity of the integrated microlens MUTC-PD increased by 66.76 % when horizontally offset by 10 μm compared to the non-integrated microlens case. When shifted vertically by 20 μm, the MUTC-PD responsivity of the integrated microlens decreases to 83.7 % of the maximum value, which is 18.2 % higher than that of the one without integrated microlens.

Efficient access to non-damaging GaN (0001) by inductively coupled plasma etching and chemical–mechanical polishing

As third-generation semiconductors advance, gallium nitride (GaN)-based devices are gaining significant attention. However, the processing of GaN substrates directly affects device performance. This paper proposes an ICP etching-chemical–mechanical polishing (CMP) strategy to efficiently produce GaN single-crystal substrates with non-destructive, atomic-level surfaces. The process time is significantly reduced from 15 h to 1.5 h. The wet oxidation reaction during CMP eliminates impurities and defects from dry etching. FIB-STEM tests confirm that this method is non-destructive, as the ICP technique enables isotropic etching, and CMP introduces no new damage to the substrate. This approach enhances the productivity of large-size GaN single-crystal substrates, promoting their broader application in laser displays, RF devices, and power electronics.

Controlled lateral positioning of NV centres in diamond by CVD overgrowth

A challenge to this day in the development of diamond devices for quantum applications is the laterally defined and closely spaced positioning of nitrogen-vacancy centres with exceptional coherence properties. Here, we demonstrate a maskless, implantation-free method for the controlled in-plane positioning of NV centres using a combination of focused ion beam (FIB) milling, plasma etching and nitrogen-doped diamond growth. The Ga+ ion beam milling resulted in 1 μm × 1 μm cavities with depths of up to 450 nm, each cavity exhibiting the four [111]-oriented diamond facets after pure hydrogen plasma treatment and a depth of 700 nm. Low-methane, nitrogen-doped chemical vapour deposition (CVD) overgrowth resulted in in situ formation of oriented NV ensembles, exclusively perpendicular to the {111}-planes.

In Situ Dewetting Assisted Plasma Etching of Large‐Scale Uniform Nanocones on Arbitrarily Structured Glass Elements

AbstractNanocones are ideal for wide‐angle antireflection of glass elements, yet their applications often encounter complex geometries and large sizes, bringing serious difficulty in developing a reliable and efficient manufacturing process. Here, an in situ dewetting assisted plasma etching (In situ DAPE) method is proposed to engrave nanocones on arbitrarily structured glass elements in one step. While exposed to high‐energy plasma, pre‐sputtered platinum (Pt) film undergoes dewetting, forming uniformly distributed nanoparticles that act as in situ sacrificial masks for plasma etching to generate nanocones. The nanocone size is decided by nanoparticle size, which can be modified through the Marangoni effect of the melted Pt film. Incorporating a passivation step can improve the aspect ratio of nanocones up to ≈8:1 due to the trench effect. Nanocones with diameters ranging from 62 to 136 nm and heights from 126 to 942 nm can be achieved. The nanocones help to achieve an average transmittance of 98% over the 0.3–2.5 µm spectrum and a 79.4% laser‐induced damage threshold of bare fused silica. The efficient fabrication of nanocones over multiple glass elements is demonstrated including a 2‐inch flat window, cylindrical microlens array, and diffractive grating, highlighting the efficacy of the In situ DAPE method for high‐performance optical elements.

Examination of nonideal film growth in batch atomic layer deposition for plasma-resistant coatings

Atomic layer deposition (ALD) can be used to fabricate protective coatings including moisture barrier layers for organic light emitting diodes, anticorrosion layers for photoelectrodes, and plasma-resistant coating for semiconductor manufacturing equipment, which necessitates the deposition of large and thick ALD films via batch ALD. However, batch ALD for the fabrication of large-area and thick coatings exhibits nonideal film growth, a phenomenon that cannot solely be explained by transient concentration distribution within the deposition chamber. This paper describes the application of precursor “exposure” (in the unit of Langmuir, or Pa s), defined as the integral of concentration over time, as a metric to assess the growth per cycle (GPC) distribution under nonideal ALD conditions, demonstrating that the local GPC correlates well with the cumulative precursor exposure at that site. Consequently, this measure can effectively predict the nonuniformity (NU) distribution of film thickness and facilitate the determination of optimal operating conditions that ensure maximal uniformity of exposure. Under this condition, the intrafilm NU of ALD-grown Al2O3 film (nominal thickness 300 nm) was reduced to 1.2%, and the interfilm NU is diminished to as low as 3.3%. These values represent reductions of 40% and 45%, respectively, compared to the NU levels observed under nonideal conditions (insufficient trimethylaluminum, TMA exposure downstream). The plasma etch rate of ALD-deposited films is merely 4.3 nm/min, representing a reduction of one-half compared to films deposited under nonideal conditions (9.8 nm/min) with overload TMA exposure downstream leading to chemical vapor deposition-like reactions.

Formation of YOF on Y2O3 through surface modification with NH4F and its plasma-resistance behavior

Yttrium oxyfluoride (YOF) is known for exhibiting superior plasma-resistance properties compared to Y2O3, particularly in a fluorocarbon plasma environment. The formation of the YOF layer directly on the surface of Y2O3 via surface modification may be considered as a viable and cost-effective method. In this study, we employed ammonium fluoride (NH4F) salt for the surface modification of Y2O3. By using a 40 wt% NH4F aqueous salt solution, the YOF layer with a thickness of about 8.6 μm was efficaciously formed in-situ on the surface of Y2O3 based on the fluorination mechanism. The composition and microstructure of the modified Y2O3 surface was thoroughly characterized using X-ray diffraction (XRD) and scanning electron microscopy (SEM). XRD analysis revealed the formation of distinct intermediate ammonium yttrium fluoride phases depending upon the heat treatment temperature (150 − 500 °C) through the fluorination of Y2O3 with NH4F. A stable YOF phase was formed ultimately at 300 °C. Plasma etching tests were performed using a mixture of CF4/Ar/O2 gases for 1 h. The microstructures of specimens are observed by SEM before and after plasma treatments. Plasma exposure tests demonstrated that specimens heat-treated at 500 °C for 2 h exhibit excellent plasma-resistance behavior with minimal surface damage, which is attributed to the presence of stable and dense YOF phase.

Study on the performance of InGaN-based micro-LED by plasma etching combined with ion implantation process

This study utilized blue-light epitaxial wafers and employed semiconductor processes such as maskless laser writing, dry etching, wet etching, passivation layer deposition, electron beam evaporation, and ion implantation to fabricate micro-light emitting diode (μLED) arrays with different pixel sizes but the same emitting area (900 μm²). The μLED arrays with single pixel sizes of 5 μm, 10 μm, and 15 μm were fabricated, with array numbers of 6×6, 3×3, and 2×2, respectively. This study proposes etching the material in the channel region while retaining a certain width for implantation, known as the sidewall ion implantation process, aiming to achieve better insulation characteristics by using ion implantation technology to insulate the sidewall regions. It involves ion bombardment of the defect areas generated after plasma etching and the use of a passivation layer for protection. The isolation characteristics of μLED arrays processed by sidewall implantation exhibited better electrical isolation than those of μLED arrays processed only by plasma. The light output power, external quantum efficiency, and wall-plug efficiency were all superior for the sidewall implantation process when the device was miniaturized to 5 μm. Overall, the sidewall implantation process combined with plasma dry etching effectively improved the light output characteristics, with the enhancement ratio increasing as the device was miniaturized.

Transfer of micron pattern with reactive atmospheric plasma jets into fused silica

Pattern transfer by plasma etching is a traditional standard technology in microelectronics and other micron technologies. These technologies require vacuum conditions, which limit throughput, size, and low-cost fabrication. Recent developments in low cost atmospheric plasma technologies may be suitable to realize pattern transfer without vacuum conditions. Reactive atmospheric plasma jet etching has been used to transfer aluminum mask patterns to fused silica. Aluminum line patterns of 2.5 to 50 µm width on fused silica wafer are exposed to a static as well as a scanning CF4/O2 reactive atmospheric plasma jet with a footprint diameter of 0.85 mm (full width at half maximum), resulting in etching only the SiO2 and causing a nearly isotropic etch with an etch rate of about 200 nm/s. As a result, line narrowing, trapezoidal line cross-sections, and under-etching were observed. The successfully transferred line patterns with the demonstrated widths and depths are of technological interest in various fields of application. Therefore, this approach enables low-cost patterning of fused silica through the use of reactive atmospheric plasma jet etching for micron-scale pattern transfer. This advancement addresses the limitations of both traditional vacuum-based and wet etching methods.

The impact of pulsed Nd:YAG laser on the surface of n-Si and photo-electrical performance of silicon solar cells

Texturizing the surface of a silicon solar cell enhances performance by reducing reflection losses. Pyramidal texturization via wet chemical etching is standard in manufacturing, while plasma etching is often used for vertical hole texturization. Laser texturization offers a chemical-free, user-friendly alternative to plasma etching. Infrared (IR) transmission studies indicate that laser-textured samples transmit more IR light through n-Si than normally textured samples, suggesting that vertical grooves from laser texturization allow deeper light penetration. Analyses using cross-sectional Field Emission Scanning Electron Microscopy (FESEM), Energy Dispersion x-ray (EDX), and Energy Dispersive Spectroscopy (EDS) demonstrate the effects of laser texturization on the front surface of textured n-Si wafers. However, silicon solar cells with laser-textured surfaces demonstrated lower conversion efficiencies (1.20% to 4.30%) compared to conventionally textured cells (14.30%). The short-circuit current density (JSC) was also lower in laser-textured cells, below 17 mA cm−2, compared to 34.44 mA cm−2 in normally textured cells. At the same time, higher laser power (114 W) during texturization also led to the lowest JSC and open-circuit voltage (VOC), indicating that laser texturization may introduce defects and dislocations that degrade Si properties.

Microstructure and corrosion resistance of novel rare-earth-zirconia doped Y2O3 plasma-sprayed coating

Y2O3 coatings are widely applied in semiconductor etching machines to protect the inner walls of aluminum alloys. This study reports the preparation of yttria-based coatings on aluminum alloy substrates using atmospheric laminar plasma spraying (ALPS) methods. In this study, four yttria-based coatings were designed and tested for their thermal performance, plasma etching resistance, and resistance to laser ablation. The rare-earth-zirconia (RE-ZrO2) doped Y2O3 coating exhibited the best thermal insulation performance, with a thermal conductivity of approximately 0.6 W m−1 k−1 at 600 °C. Plasma etching experiments demonstrated that more rare-earth fluorides were generated on the surface of the RE-ZrO2 doped Y2O3 coating, which weakened the plasma energy. Finally, the lowest etching rate was achieved. Laser ablation experiments demonstrated that the depth of the ablation pit on the surface of the RE-ZrO2 doped Y2O3 coating was shallow, indicating good laser ablation resistance. These results indicate that rare-earth-doped yttria-based coatings provide excellent corrosion protection against plasma etching and laser ablation.

The Etching Behaviour and Fluorine-Based-Plasma Resistance of YOF Coatings Deposited by Atmospheric Plasma Spraying

There is a high demand for plasma-resistant coatings that prevent the corrosion of the internal ceramic components of plasma etching equipment, thereby reducing particle contamination and process drift. Yttrium oxyfluoride (YOF) coatings were prepared using atmospheric plasma spraying (APS) with commercially available YOF/YF3 powder mixtures; namely YOF 3%, YOF 6%, and YOF 9%. The etching behaviour of YOF and yttrium oxide (Y2O3) coatings was investigated using an inductively coupled plasma consisting of NF3/He. X-ray photoelectron spectroscopy (XPS) showed that the YOF 6% coating had the thickest fluorinated layer. The scanning electron microscope (SEM) examination revealed that the YOF 6% coating showed exceptional resistance to erosion and generated a reduced quantity of contaminated particles in comparison to Y2O3. Consequently, it is more suitable as a protective material for the inner wall of reactors. The YOF coatings exhibit excellent stability and high resistance to erosion, indicating their appropriateness for use in the semiconductor industry.

Research and Analysis on Enhancement of Surface Flashover Performance of Epoxy Resin Based on Dielectric Barrier Discharge Plasma Fluorination Modification.

To conquer the challenges of charge accumulation and surface flashover in epoxy resin under direct current (DC) electric fields, numerous efforts have been made to research dielectric barrier discharge (DBD) plasma treatments using CF4/Ar as the medium gas, which has proven effective in improving surface flashover voltage. However, despite being an efficient plasma etching medium, SF6/Ar has remained largely unexplored. In this work, we constructed a DBD plasma device with an SF6/Ar gas medium and explored the influence of processing times and gas flow rates on the morphology and surface flashover voltage of epoxy resin. The surface morphology observed by SEM indicates that the degree of plasma etching intensifies with processing time and gas flow rate, and the quantitative characterization of AFM indicates a maximum roughness of 144 nm after 3 min of treatment. Flashover test results show that at 2 min of processing time, the surface flashover voltage reached a maximum of 19.02 kV/mm, which is 25.49% higher than that of the untreated sample and previously reported works. In addition to the effect of surface roughness, charge trap distribution shows that fluorinated groups help to deepen the trap energy levels and density. The optimal modification was achieved at a gas flow rate of 3.5 slm coupled with 2 min of processing time. Furthermore, density functional theory (DFT) calculations reveal that fluorination introduces additional electron traps (0.29 eV) and hole traps (0.38 eV), enhancing the capture of charge carriers and suppressing surface flashover.

NiCo layered double hydroxide nanosheet arrays constructed via in-situ plasma etching as non-enzymatic electrochemical sensor for glucose in food

The design and construction of an efficient non-enzymatic glucose electrochemical sensor is of great significance for food quality assessment. Here, we have developed a method to fabricate highly efficient catalytic electrodes for glucose sensing in alkaline. This method utilizes microplasma assistance during the in-situ etching of NiCo layered double hydroxide nanosheet arrays on nickel foam (NiCo-LDH/NF). The NiCo-LDH nanosheets possessed uniform dispersion without agglomeration, high electrochemically active surface area, and excellent electron transfer efficiency (the electron transfer coefficient (α) up to 0.91, the catalytic rate constant (k) was 2.44 × 106 cm3 mol−1 s−1). The NiCo-LDH/NF-based non-enzymatic glucose sensor exhibits the broad linear range (0.4–150 μM), high sensitivity (98000 μA mM−1 cm−2), and the low detection limits (48.76 nM) with satisfactory reproducibility and selectivity. This work developed a simple and rapid in-situ approach for constructing non-enzymatic electrochemical sensors with high sensitivity.

Dicing Process for 4H-SiC Wafers by Plasma Etching Using High-Pressure SF<sub>6</sub> Plasma with Metal Masks

Since SiC is hard and brittle, dicing by normal grinding process not only requires a long time for processing, but also reduces chip strength due to microcracks. The use of highly efficient and damage-free etching with high-pressure plasma as a chemical processing method for dicing rather than mechanical processing was investigated. The results of groove processing using a combination of a metal mask with slit-like apertures and plasma etching with high-pressure SF6 plasma showed that the processing speed decreased with decreasing slit width and increasing groove depth. The results of electrostatic field calculations suggest that this is due to a decrease in plasma intensity caused by electric field decreasing.

Enhanced etching of GaN with N2 gas addition during CVD diamond growth

Diamond on GaN materials processing is not straight-forward, as GaN is susceptible to a quasi-pure hydrogen CVD plasma etching. 1%, 3% and 5% N2 gas was gradually added to the H2 gas with fixed 6% CH4 in the recipe to promote the growth of diamond nanocrystals. Different types of microstructures were produced, with addition of nitrogen to the precursor gas recipe. Nitrogen gas changes the diamond film microstructure from faceted to spherical grains, with signs of GaN etching. The FWHM of the sp3 carbon Raman peak was calculated to be 6.5 cm−1, when there was no nitrogen gas in the precursor recipe, which deteriorates to a large extent after successive addition of N2. Fourier transform infrared spectroscopy (FTIR) showed a strong presence of the nitrogen related defects (peak positions at 1190 and 1299 cm−1) inside the nanocrystalline diamond (NCD) films grown with N2 addition. GaN layer etching from the base substrate by the CVD plasma was clearly evidenced by energy dispersive X-ray spectra (EDS) of the deposited films. Al elemental EDS peaks from the base sapphire substrate were observed for the films grown with nitrogen addition, but no Ga EDS peaks were detected. X-ray diffraction (XRD) micrographs further supported the enhanced GaN etching phenomenon. The electrical resistivity of the uncoated GaN was initially measured to be 22.2 Ω-cm. However, the resistivity rose to 1.59 × 106 Ω-cm after the nitrogen assisted film deposition; due to the GaN etching - thereby exposing the underlying insulating sapphire substrate.

Novel and Low-Cost Techniques for Extending the Etch Capabilities of an Inductively Coupled Plasma Etch Tool That Has Clamp Fingers for Clamping 4-Inch Diameter Wafers

Widening the processing capabilities of an inductively coupled plasma (ICP) etch tool by “preventing wafer breakage” during processing of wafers, or by gaining the capability to do “through-wafer silicon etch” are important challenges that may need to be resolved with very limited resources. Resolving the undesired wafer breakage issues caused during processing of wafers is important to reduce the manufacturing costs, and increase production yield. Furthermore, considering the high prices of the state-of-the-art wafer processing tools, it is also important to prevent wafer breakage by using low-cost approaches especially if the resources for purchasing state-of-the-art processing equipment are not available. Two novel methods (method #1, and method #2) are developed to prevent wafer breakage and allow through-wafer silicon etching. With method #1, an aluminium alloy ring (AAR) and an o-ring are employed to obtain uniform load distribution (instead of point loads) on the required outer region on the surface of a wafer, and to minimize or completely remove the bending moment that may be formed on the possible cross-sections of the entire wafer, during clamping of the wafer. With method #2, through-wafer silicon etching is made possible by simultaneous application of method #1 and addition of a helium cooling gas (HCG) leakage blocking dicing tape at the back side of the wafer that is under processing for through-wafer etching. By using the explained methods, wafer breakage during ICP etch processing is eliminated, and through-wafer silicon etching is made possible. From the other side, the effective wafer area that can be used for processing is reduced by 48%. Novel and capability enabling 2 different techniques that are extremely low-cost compared to purchasing a state-of-the-art ICP etch tool are presented to extend the processing capabilities of an ICP etch tool for deep silicon etching (method #1), and through-wafer silicon etching (method #2).

Selective Isotropic Dry Etching of SiO2 Using F/H-Based Pulsed Remote Plasma and a Vapor Phase Solvent

Isotropic etching generally employs liquid-based wet etching techniques. However, due to the high integration of devices, conformal etching is challenging in patterns with a high aspect ratio because liquid chemicals struggle to penetrate inside the pattern. Additionally, during the drying process after chemical treatment, pattern collapse is observed due to surface tension. Therefore, there is a need for dry isotropic etching techniques to replace wet etching techniques in next-generation device manufacturing processes.Typically, when high selectivity SiO2 isotropic dry etching is required, F-base/H-based gas mixtures are utilized to form HF, which serves as an etchant for SiO2. SiO2 can be dry etched through two different mechanisms. First, HF reacts directly with H2O or alcohol, etching SiO2. The other way is to produce (NH4)2SiF6 salt from the reaction of NH3, which can be formed in a plasma containing NH3 and NF3. This (NH4)2SiF6 salt is sublimated and removed by a following heating process at a temperature over 100ºC.The process above has some disadvantages, such as lowering the etch selectivity of SiO2 over Si and Si3N4 because Si and Si3N4 can be etched by F radicals remaining in the plasma. This study aimed to overcome these disadvantages by controlling the F radical through pulsing the remote plasma during the discharging of F-based/H-based gas mixtures for the formation of HF. By pulsing the remote plasma, SiO2 could be selectively etched at a higher etch rate relative to those of Si and Si3N4. Additionally, various types of H/F-based gas mixtures that do not contain nitrogen while producing HF were investigated to prevent the formation of ammonium powders, which can be a source of contamination in the chamber. Futhermore, the etching mechanisms were identified through gas phase anlysis and surface analysis. Also, any possible surface damage during the etching process was investigated.

An AC and DC Electric Field Effect Based Charged Particle Focusing Scheme for Particle Beam Mass Spectrometer

Particle Beam Mass Spectrometer (PBMS) is a mass analyzer based particle sizer, features a few to hundreds of nanometer (nm) sizing capabilities in environmental pressures above hundreds of mTorr. The above feature makes the PBMS be used as in-situ process monitoring schemes for several kinds of semiconductor process equipment (e.g. Chemical Vapor Deposition). However, it still cannot be used in other process equipment (e.g. Plasma etching, Ion implantation) which requires lower process pressure conditions than the PBMS operation limits. The bottleneck of pressure limits comes from an aerodynamic lens component, which focuses incoming particles in background gas using repetitive fluidic contraction and expansion effects. These effects hard to be happened when the target particles are surrounded in molecular or transition background gas regions. In order to lower the operating pressure limits, other focusing schemes are required.In this study, an alternative particle focusing scheme which uses AC and DC electric field effects is proposed. The proposed scheme uses a stacked-ring ion funnel structure with variable AC and DC electric sources, for driving AC and DC potential variations along the funnel’s axial direction. While radial electric potential wells produced by AC frequency components induce particles’ radial position concentration to the funnel axis center, potential well depth and axial well depth steepness is controlled by AC amplitudes and DC source values.Simulation results show that with the proposed scheme, more than 50% of particle transmission efficiencies are obtained for 5 nm – 100 nm sized charged particles moving with Maxwellian velocities in molecular background region. The results come from AC electric sources with 200 Hz - 20 kHz frequency ranges and within 50 V amplitude ranges, and DC electric sources within 50 V ranges which are feasible values for hardware implementation.

A New Integration Scheme to Prevent Chemical Attack on Floating Polysilicon Gate of Non-Volatile Memory

Silicon pitting has been observed on floating gate polysilicon layer of embedded non-volatile memory(e-NVM) process due to chemical attack caused by HBr residual interacting with moisture. This paper successfully demonstrates a new integration scheme for a robust floating gate process against silicon attack for embedded stacked/split gate non-volatile memory process. Firstly, CF4 was introduced into floating gate polysilicon etch recipe to replace HBr, which has been CMOS gate polysilicon etch gas in traditional logic process due to the advantage of higher selectivity despite the disadvantage of low vaporability, for better or cleaner process control. Secondly, an additional plasma removal stripping (PRS) clean step was added before chemical removal stripping (CRS) to give better etch by-product cleaning, even though there is no photoresist and lithography involved on the poly blanket etch for the better etch by-product cleaning. This new scheme has been verified using inline optical inspection defect-scan to prove the sufficient process margin for better mass production control that came from improved manufacturing Queue-time margin (longer waiting time) between dry-etch step, CRS step, and subsequent downstream process steps. Keywords—Flash Memory, NVM, Floating Gate, HBr, Plasma Etching, Q-time, Chemical Attack, Silicon Pitting