Plasma Dry Etching Research Articles

Comparison of Two Types of Recessed-Gate Normally-Off AlGaN/GaN Heterostructure Field Effect Transistors

In this report, two types of normally-off AlGaN/GaN heterostructure field effect transistors (HFETs) with recessed-gate structure have been fabricated by using common technique of induced coupled plasma (ICP) dry etching and a novel technique of selective area growth (SAG), respectively. The devices fabricated by SAG (SAG-HFET) showed better performance than that of ICP-HFETs with larger maximum drain current of 300 mA/mm, positive threshold voltage of 0.4 V, and lower pinch off channel leakage current (2.17×10-3 mA/mm). The analysis indicates that such obvious difference originated from the different AlGaN quality of the gate region under the Schottky contact, in which the damage to the gate region stemmed from dry etching can be avoided by the SAG technique so that the forming of higher quality Schottky contact can be guaranteed. These results indicate that SAG technique is a promising method for fabricating the normally-off GaN based HFETs.

Improved Cleaning Process for Etch Residue Removal in an Advanced Copper/Low-k Device without the Use of DMAC (Dimethylacetamide)

Plasma dry etching processes are commonly used to fabricate sidewalls of trenches and vias for copper / low-k dual damascene devices. Typically, some polymers remain in the trench and at the via top and sidewall. Other particulate etch residues are may remained in the bottom and on the sidewalls of vias. Generally, the particulate consists of mixtures of copper oxide with polymers. The polymers on the sidewalls and the particulate residues at the bottom of vias must be removed prior to the next process step. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the etching in order to achieve a vertical profile and to protect the low-k materials under the etching mask. Until now, the industry has relied mainly on organic solvent containing mixtures to clean etch / ash residues from such devices. The effectiveness of available residue removers varies with the specific process and also depends on which new integration materials are used. New materials typically include Cu, TaN, low-k dielectrics and others [1-. Solvent content is thought to aid the removal of polymer residues and particulates produced during plasma dry etching processes. Therefore, in the past we have used a residue remover which contains DMAC (dimethylacetamide). But the use of DMAC is banned in microelectronic fabrication facilities in Europe because of its toxicity. Thus we wanted to find and evaluate a DMAC-free residue remover for removing polymer residues while maintaining high selectivity to the copper and ILD films.

Nanostructuring of silicon substrates for the site-controlled growth of GaAs/In0.15Ga0.85As/GaAs nanostructures

We report the optimization of electron beam lithography and inductively coupled plasma (ICP) dry etching processes to fabricate pre-patterned Si (100) substrates with sub-100nm holes with controlled size and shape. An efficient in situ cleaning sequence based on atomic hydrogen cleaning at 500^oC combined with thermal oxide desorption at 750^oC confirmed by reflection high energy electron diffraction (RHEED) pattern of two dimensional clean surface prior to the MBE growth has been established. The MBE growth of GaAs/In0.15Ga0.85As/GaAs system on patterned Si surface has shown highly selective formation of localized dome like nanostructures in patterned holes with [email protected] period.

Controlled oxidative functionalization of monolayer graphene by water-vapor plasma etching

We report studies on the controlled step-by-step oxidative functionalization of monolayer graphene by chemically reactive water-vapor plasma dry etching. The use of a porous mask on top of the graphene sheets as a filter is essential to reduce the density of free radicals and weaken the sputtering effect. Micro-Raman spectroscopy, X-ray photoelectron spectroscopy and atomic force microscopy showed that the oxidation occurred in a mild and controllable way, and that a wide variety of oxygen-containing functional groups can be evenly and incrementally incorporated onto the carbon lattice. By monitoring the electrical property changes in the graphene at different levels of oxidation, we observed a transformation of the electrical conduction process from continuum percolation to variable range hopping and/or electric-field-driven tunneling, due to the progressive increase of sp3-based basal plane distortion that disrupts the transport of carriers delocalized in the sp2 carbon network.

선택성장영역 크기에 따른 InGaN/GaN 다중양자우물 청색 MOCVD-발광다이오드 소자의 특성

(Received October 12, 2011)(Revised October 24, 2011)(Accepted November 11, 2011)Abstract In general, the fabrications of the LEDs with mesa structure are performed grown by MOCVD method. In orderto etch and separate each chips, the LEDs are passed the RIE and scribing processes. The RIE process using plasma dryetching occur some problems such as defects, dislocations and the formation of dangling bond in surface result in declineof device characteristic. The SAG method has attracted considerable interest for the growth of high quality GaN epi layeron the sapphire substrate. In this paper, the SAG method was introduced for simplification and fabrication of the highquality epi layer. And we report that the size of selective area do not affect the characteristics of original LED. Thediameter of SAG circle patterns were choose as 2500, 1000, 350, and 200µm. The SAG-LEDs were measured to obtainthe device characteristics using by SEM, EL and I-V. The main emission peaks of 2500, 1000, 350, and 200µm were 485,480, 450, and 445 nm respectively. The chips of 350, 200µm diameter were observed non-uniform surface and resistancewas higher than original LED, however, the chips of 2500, 1000µm diameter had uniform surface and current-voltagecharacteristics were better than small sizes. Therefore, we suggest that the suitable diameter which do not affect thecharacteristic of original LED is more than 1000µm.Key wordsSelective area growth, InGaN/GaN, Multi quantum well, MOCVD, Band-filling effect, Screening effect

Perfectly notched long-period fiber grating filter based on ICP dry etching technique

This study presents a new process using inductively a coupled plasma dry etching method to manufacture a long-period fiber grating filter with exact period, vertical sidewalls, and smooth etched surfaces, and the filter is thus named a perfectly notched long-period fiber grating (NLPFG). This process can dramatically reduce production time, and thereby provide higher volume production. The fabricated NLPFG has periods of 640 μm, resonant-attenuation wavelengths of 1518 nm, and maximum resonance-attenuation of 21.79 dB. A force induced loss-tunable calibration of the NLPFG filter was implemented, and a monotonically increasing quadratic fitting was observed. The results demonstrated that the proposed NLPFG has a much better period precision compared to corrugated LPFG, and it has great potential for a loss-tunable filter and force transducer applications.

Ge quantum dots light-emitting devices

Si photonics becomes one of the research focuses in the field of photonics. Si-based light-emitting devices are one of the most important devices in this field. In this paper, we review the Si-based light-emitting devices fabricated by embedding Ge self-assembled quantum dots into optical microcavities. Ge self-assembled quantum dots emit light in the telecommunication wavelength range from 1.3 to 1.6 μm, for which Si is transparent. Ge self-assembled quantum dots were grown on silicon-oninsulator (SOI) by molecular beam epitaxy (MBE) in Stranski-Krastanov (S-K) mode. Then, electron beam lithography (EBL) was used to define the pattern of optical microcavities on the wafer. Finally, the pattern was transferred onto the Si/Ge slab by inductive coupled plasma (ICP) dry etching. Room-temperature photoluminescence (PL) was used to characterize the light-emitting properties of fabricated devices. The results showed that strong resonant light emission was observed in different optical microcavities. Significant enhancement of the intensity was obtained by the optical resonance. Based on the results of PL, we designed and fabricated current-injected light-emitting devices based on Ge self-assembled quantum dots in optical microcavities. Room-temperature resonant light emission was observed from Ge dots in a 3.8 μm microdisk resonator.

Improved spectral characteristics of 980 nm broad area slotted Fabry—Perot diode lasers

A novel broad area slotted Fabry—Perot diode laser is designed and fabricated. Using a new semi-analytical method, we introduce effective refractive index perturbations in the form of etched slot features into a conventional 980 nm broad area Fabry—Perot cavity, and the spectral characteristics of the device are expected to be noticeably improved. A low density of slot features is formed by using standard optical lithography and inductively coupled plasma dry etching. The experimental results show that the full spectral width at half-maximum is less than 0.4 nm, meanwhile, the thermal shift of the emission spectrum is decreased from 0.26 to 0.07 nm/°C over a temperature range of 10 to 60 °C. The improved spectral characteristics of the device are proved to be attributed to such slotted Fabry—Perot laser structures.

Wide-angle antireflection ZnO films on bullet-like nanostructures of multi-crystalline silicon

Nanosphere lithography and antireflection coating techniques have been applied to fabricate wide-angle antireflection structures on multicrystalline silicon substrates. Self-assembled 550-nm SiO2 nanospheres were arranged periodically to act as a mask to block the inductively coupled plasma dry etching and form bulletlike nanostructures on the surface of the multicrystalline silicon wafer. Then a 65-nm-thick zinc oxide film was deposited on the nanostructures using the atomic layer deposition method. The results show that when applying the nanostructure with a ZnO film the average reflectivity of the multicrystalline silicon wafer can be decreased from 36% to 0.65% in the wavelength range from 400 nm to 850 nm for an incident angle of 8°. When the incident angle reaches 60° the average reflectivity of the sample becomes less than 4.6%.

Direct fabrication of two-dimensional photonic crystal structures in silicon using positive and negative Hydrogen Silsesquioxane (HSQ) patterns

The use of Hydrogen Silsesquioxane (HSQ) as a negative-tone electron-beam resist and a hard etching mask to directly fabricate two-dimensional Si-based photonic crystals (PhC) was investigated. We demonstrate a protocol using the HSQ resist, including spin coating processes, low-energy electron-beam exposures, development, post-development treatments, and dry-etching, to achieve sub-micron two-dimensional photonic crystal structures in silicon. An electron-beam area dose of 315@mC/cm^2 at 30kV was sufficient to produce anisotropic 267-nm deep HSQ-based PhC features upon development. Subsequent oxygen plasma treatment and dry etching processes were done to transfer the final patterns to the underlying silicon with a 1:1.23 etch selectivity (Si:HSQ) using a CF4/O2 plasma. These results demonstrate the use of HSQ to simplify the fabrication processes for photonic crystals and their integration with other optical-based on-chip components.

PMN–PT (lead magnesium niobate–lead titanate) piezoelectric material micromachining by excimer laser ablation and dry etching (DRIE)

In the attempt to find the appropriate micromanufacturing technology of PMN–PT (lead magnesium niobate–lead titanate) piezo material, whose MEMS-related applications look promising, two methods are investigated: excimer laser ablation (using KrF gas) and inductively coupled plasma (ICP) dry etching, also known as DRIE (using Ar/C4F8 gases). The paper quantitatively reports the optimal parameters for PMN–PT micromachining and compares both methods. KrF excimer laser ablation threshold fluence is of 14J/cm2, the etching rate may reach 100μm/min (50nm/pulse) but the ablated surfaces are cone-shaped restricting thus the method to cutting/drilling 2D shapes. Excimer ablation method is found to be more convenient for rapid prototyping with less precise features requirements (>10μm). On the other hand DRIE method on PMN–PT is time-consuming, requires a hard mask deposition but is cleaner and more precise. Dry etching maximum recorded speed is of 0.19μm/min. The nickel hard mask selectivity varies around 8:1. In exchange this method provides flatter surfaces with no etched material redeposition.

Influence of Wafer Grinding and Etching Techniques on the Fracture Strength of Thin Silicon Substrates

We investigated the influence of various backside thinning techniques on the fracture strength of thinned single crystalline silicon wafers by means of ring-ball breaking tests and atomic force microscopy (AFM). In the case of wafer grinding the mean breaking force of samples depends on the surface roughness after fine grinding. Subsequently applied stress-relief processes spin-etching, CMP polishing and plasma dry etching lead to a strong increase of breaking force by a factor of 6 to 15. The three different stress-relief techniques resulted in the same maximum values of breaking force. However, the required amount of material removal is specifically different and also depends on the conditions of initial grinding step. The results will help to identify optimum wafer thinning sequences in the field of MEMS devices and future applications of ultra-thin and flexible integrated circuits.

Optimization of initial MOVPE growth of non‐polar m‐ and a‐plane GaN on Na flux grown LPE‐GaN substrates

AbstractWe optimized the initial GaN growths of nonpolar m‐ and a‐plane GaN grown on liquid phase epitaxy (LPE‐) GaN substrates. Such nonpolar LPE‐GaN substrates were produced by cutting slices from c‐plane LPE‐GaN bulk single crystals grown by the Na‐flux method. We investigated the qualities of epitaxially grown GaN layers on the LPE‐GaN substrates, with different polishing methods, which are chemical mechanical polishing and plasma dry etch polishing. We found that the crystalline quality of epitaxial GaN on m‐plane GaN is very sensitive to the surface polishing even the minute unevenness in GaN substrate. Our experiments also indicated that a low initial growth rate was necessary to obtain high‐crystalline‐quality epitaxial m‐plane GaN. In contrast, high‐crystalline‐quality a‐plane GaN was obtained even with a high initial growth rate, indicating that the crystalline quality of a‐plane GaN is not sensitive to surface roughness. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Double-Step Plasma Etching for SiO<sub>2</sub> Microcantilever Release

In this paper, an isotropic dry plasma etching was used to release the suspended SiO2 microcantilever from the substrate of SOI wafer. Employing the plasma dry etching technique, the frontside etching for the SiO2 microcantilever release is done using the Oxford Plasmalab System 100. To obtain the optimum condition for the microcantilever release using the plasma etcher, the etching parameters involved are 100 sccm of SF6 flow, 2000 W of capacitively coupled plasma (CCP) power, 3 W of inductively coupled plasma (ICP) power, 20°C of etching temperature and 30 mTorr chamber pressure. The optimum parameters yield lateral etch rate of about 5 μm/min and vertical etch rate of about 8 μm/min. Two etching methods have been considered in this study. The first method employs only the isotropic etching to realize the microcantilever release while the second method utilizes both the anisotropic etching and the isotropic etching. For the second method, the process starts with the anisotropic etching from the deep reactive ion etching (DRIE) system which is then followed by the isotropic etching to complete the microcantilever releasing process. The purpose of the anisotropic etching is to create an etching window for the subsequent isotropic etching process. By using double-step etching method which combines both isotropic and anisotropic plasma etching for the microcantilever release process, the releasing process of suspended microcantilever is significantly improved.

Study on leakage current of pn diode on GaN substrate at reverse bias

AbstractIn this paper, we studied on a leakage current of a pn diode on a GaN substrate isolated by a mesa structure at a reverse bias. The leakage current flowed at a surface of the mesa sidewall across the pn junction. Results of scanning capacitance microscopy and scanning spread resistance microscopy indicated that the surface of the mesa sidewall in the p type region changed to a depleted or a n‐‐layer. Results of auger electron spectroscopy indicated that a concentration of nitrogen decreased near the surface of the mesa sidewall. From these results, we estimated the leakage current was caused by a change of the p type region at the surface of the mesa sidewall to the depleted or n‐‐layer by inductively coupled plasma dry etching, which was used to form the mesa structure. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

1A2-C02(1) ガラスナノ・マイクロ加工の表面特性への影響(ナノ・マイクロ流体システム)

Research of biochemical analysis system using micro/nano flow channel and fluid device has been ongoing actively. In micro/nano flow channel, effect of surface condition is larger than that of normal scale. Thus, physical or chemical characteristics such as surface roughness, zeta potential largely affect a system. In this paper, we used hydrofluoric acid, plasma dry etching and machining to etch glass surface. We measured the relation between time and etching depth, and successfully indicated the relation between etching depth and surface roughness or zeta potential.

Enhancing fracture strength of thinned silicon dies by a hybrid micromachining method

The fracture strength of silicon wafers is crucial in determining the manufacturing yield, operational reliability and device performance of semiconductor components. Many researches have shown the surface finishing and stress release treatments such as wet etching, dry (plasma) etching, polishing, etc., can effectively improve the fracture strength of thinned silicon dies. In this paper, a novel hybrid micromachining method that integrates super-precision grinding process, backside rough finish etching, and backside metal deposition process, is studied with experimental investigation with an aim to improve the fracture strength of thinned silicon dies. The experimental results are shown to enhance the fracture strength by approximately 150% higher than the conventional grinding process with this novel method. In this way the semiconductor manufacturers have the benefits of retaining the mechanical performance as well as electrical or thermal performance of thinned silicon dies with the backside metal processing.

Direct pattern transfer using an inorganic polymer-derived silicate etch mask

Advancements in patterning materials combined with facile fabrication techniques have been critical for the development of the semiconductor industry. In order to develop a new silicate etch mask for direct pattern transfer onto silicon via etching, methacrylated polyvinylsilazane, an inorganic polymer photoresist acting as a patternable silicate precursor, was used to fabricate micron-scale patterns over a large area upon 6 inch silicon wafers by conventional photolithography. The photolithographic patterns obtained were hydrolyzed to convert the polymer phase into the silicate phase after post-heat treatment at 150 °C. The silicate patterns were transferred as an etch mask onto silicon wafers via dry plasma etching process using various ratios of an SF6/Cl2/Ar mixture as etchant. The silicate patterns revealed an excellent etching selectivity of 16 for silicon, which was 8–16 times higher than the polymer phase.

Nanotexturing of GaN light-emitting diode material through mask-less dry etching

We describe a new technique for random surface texturing of a gallium nitride (GaN)light-emitting diode wafer through a mask-less dry etch process. This involves depositing asub-monolayer film of silica nanospheres (typical diameter of 200 nm) and then subjectingthe coated wafer to a dry etch process with enhanced physical bombardment. The silicaspheres acting as nanotargets get sputtered and silica fragments are randomly deposited onthe GaN epi-layer. Subsequently, the reactive component of the dry etch plasma etchesthrough the exposed GaN surface. Silica fragments act as nanoparticles, locally maskingthe underlying GaN. The etch rate is much reduced at these sites and consequently arough topography develops. Scanning electron microscopy (SEM) and atomicforce microscopy (AFM) inspections show that random topographic features atthe scale of a few tens of nanometres are formed. Optical measurements usingangle-resolved photoluminescence show that GaN light-emitting diode material thusroughened has the capability to extract more light from within the epilayers.

Advanced HDP STI Gap-Fill Development in 65nm Logic Device

High density plasma chemical vapor deposition (HDP-CVD) has been proven to be a sucessful process for shallow trench isolation (STI) gap fill in advanced CMOS device fabrication. As CMOS technology nodes continue to shrink, STI gap-fill requirement become more and more challenging. To keep pace with the stringent requirements, a novel HDP gap-fill process - Integrated Proess Modulation (IPM) has been developed to fill these aggressive structures. IPM process, which is extending from Deposition - Etch - Deposition (DED) process, is made of a serial of deposition/etch cycles, which is one of techniques to keep trench open by using NF3-based plasma dry etch before the trench nearly closed by film deposition. Based on this process model, HDP gap-fill capability has been greatly extended to 65nm and beyond. This paper summarizes the STI gap-fill development and optimization work of IPM processes