Plasma Dry Etching Research Articles

Highly textured multi-crystalline silicon surface obtained by dry etching multi-step process

In this work we propose the use of a plasma dry etching technique to condition the morphology of a silicon surface. The low environmental impacted NF3 halogen compound is adopted together with Ar to perform a multi-step process which helps to enhance the silicon surface texturing, thus reducing the time needed for the whole dry etching procedure, which also include saw damage removal on silicon wafers. A detailed study of surface reflectance and etching rate as a function of the dry plasma process parameters is discussed to achieve suitable multi-crystalline silicon surfaces for photovoltaic applications.

Fabrication of Diamond Microstructures by Using Dry and Wet Etching Methods

Diamond films have great potential for micro-electro-mechanical system (MEMS) application. For device realization, precise patterning of diamond films at micrometer scale is indispensable. In this paper, simple and facile methods will be demonstrated for smart patterning of diamond films, in which two etching techniques, i.e., plasma dry etching and chemical wet etching (including isotropic-etching and anisotropic-etching) have been developed for obtaining diamond microstructures with different morphology demands. Free-standing diamond micro-gears and micro-combs were achieved as examples by using the experimental procedures. It is confirmed that as-designed diamond structures with a straight side wall and a distinct boundary can be fabricated effectively and efficiently by using such methods.

The performances of silicon solar cell with core–shell p-n junctions of micro-nano pillars fabricated by cesium chloride self-assembly and dry etching

Silicon micro-nano pillars are cost-efficiently integrated using twice cesium chloride (CsCl) islands lithography technique and dry etching for solar cell applications. The micro PMMA islands are fabricated by inductively coupled plasma (ICP) dry etching with micro CsCl islands as masks, and the nano CsCl islands with nano sizes then are made on the surface of micro PMMA islands and silicon. By ICP dry etching with the mask of micro PMMA islands and nano CsCl islands, the micro-nano silicon pillars are made and certain height micro pillars are randomly positioned between dense arrays of nano pillars with different morphologies by controlling etching conditions. With 300 nm depth p-n junction detected by secondary-ion mass spectrometry (SIMS), the micro pillars of the diameter about 1 μm form the core–shell p-n junction to maximize utility of p-n junction interface and enable efficient free carrier collection, and the nano tapered pillars of 150 nm diameter are used to decrease reflection by a graded-refractive-index. Compared to single micro or nano pillar arrayed cells, the co-integrated solar cell with micro and nano pillars demonstrates improved photovoltaic characteristic that is a photovoltaic conversion efficiency (PCE) of 15.35 % with a short circuit current density (J sc) of 38.40 mA/cm2 and an open circuit voltage (V oc) of 555.7 mV, which benefits from the advantages of micro-nano pillar structures and can be further improved upon process optimization.

Fabrication of the similar porous alumina silicon template for soft UV nanoimprint lithography

High density honeycombed nanostructures of porous alumina template (PAT) have been widely used to the fabrication of various electronic, optoelectronic, magnetic, and energy storage devices. However, patterning structures at sub-100nm feature size with large area and low cost is of great importance and hardness on which semiconductor manufacture technology depends. In this paper, soft UV nanoimprint lithography (SUNIL) by using PAT as the initial mold is studied in detail. The results reveal a significant incompatibility between these two candidates. The native nonflatness of the PAT surface is about 100nm in the range of 2–5μm. Resist detaches from the substrate because of the mold deformation in the nonflat SUNIL. A two-inch similar porous alumina silicon (Si) template with nanopore size of 50–100nm is fabricated. I–t curve conducted anodization and subsequent inductive coupled plasma (ICP) dry etching are applied to ensure the uniformity of the fabricated template. The surface flatness of the similar porous alumina Si template is the same as the polished Si wafer, which perfectly matches NIL.

Black silicon: substrate for laser 3D micro/nano-polymerization

We demonstrate that black silicon (b-Si) made by dry plasma etching is a promising substrate for laser three-dimensional (3D) micro/nano-polymerization. High aspect ratio Si-needles, working as sacrificial support structures, have flexibility required to relax interface stresses between substrate and the polymerized micro-/nano- objects. Surface of b-Si can be made electrically conductive by metal deposition and, at the same time, can preserve low optical reflectivity beneficial for polymerization by direct laser writing. 3D laser polymerization usually performed at the irradiation conditions close to the dielectric breakdown is possible on non-reflective and not metallic surfaces. Here we show that low reflectivity and high metallic conductivity are not counter- exclusive properties for laser polymerization. Electrical conductivity of substrate and its permeability in liquids are promising for bio- and electroplating applications.

Ultra Low-k Damage Control and k Recovery for 28nm RC Improvement

To improve resistance-capacitance delay, porous ultra low-k dielectric materials are used in advanced copper damascene integration. However, the BEOL processes often lead to low-k film damage by removing the hydrophobic groups Si-CH3, and convert partially low-k materials surface from hydrophobic to hydrophilic one. During the wet related processes, the hydrophilic porous low-k film surface is easy to absorb moisture and potentially increase k-value. In this work, we developed the processes that can maintain ultra low-k film k-value either by repairing low-k damage or by removing moistrue. Dry etch plasma process is one of the main steps to result in low-k film damage. Post etch treatment (PET) was optimized to repair porous low-k film surface due to the etch damage. This improved process with less low-k damage can significantly reduced the moisture absorption in the following wet process and improve the capacitance by about 10%. Various thermal treatments post wet and post CMP processes were studied, including temperature, gases and pressures. From our results, post wet clean heat treatment can improve capacitance by about 5% and post CMP heat treatment can improve capacitance by about 10%. To decrease moisture absorption from atmosphere after the wafers were processed thru CMP, queue time from CMP to NDC deposition also was studied and the safe specification was also defined.

A Study on the Fabrication of Nanostructures with High Aspect Ratio and Large Area Uniformity

Nanoimprint lithography (NIL), as a promising next generation lithography method, has the advantages of high throughput, sub-10-nm feature and low cost. However, the requirements, such as the structure with high aspect ratio, large area uniformity, and pattern transfer on nonflat surface, have barely been satisfied at the same time. In this study, the authors present a novel fabrication process by introducing a three-mask-layer (TML) Soft UV NIL technique which proves to be a simple and effective method. The initial mold with low aspect ratio can guarantee the imprint uniformity on large area under a high pressure in NIL. Meanwhile, high aspect ratio structure can be easily obtained due to a high etching selectivity of SiO2 to resist in O2 plasma dry etching. Using the proposed technique to fabricate 40 nm gratings with the aspect ratio as high as 6 is proved successful. Uniform photonic crystal (PC) structures with micrometer scale nonflat steps are obtained on large area. The photoluminescence enhancements of the PC light-emitting diode (LED) fabricated by the proposed method to the one with conventional process and un-patterned LED are 1.6 fold and 2.2 fold, respectively.

Photoluminescence enhancement of GaN-based LEDs structure with nano-grayscale multiple quantum wells using electron beam lithography

Photoluminescence (PL) enhancement is achieved by using a novel nano-grayscale (NGS) InGaN/GaN multiple quantum wells (MQWs) structures. NGS patterns on the n-GaN layer were fabricated with a low contrast electron beam resist by electron beam lithography and inductively coupled plasma dry etching process. The periods of NGS patterns on the n-GaN layer are 100 and 200nm. NGS InGaN/GaN MQWs structure on the n-GaN layer was realized by subsequent epitaxial growth with metalorganic vapor phase epitaxy (MOVPE). Photoluminescence studies reveal that the LEDs with NGS InGaN/GaN MQWs structures show up to 28.5% enhancement of luminescence intensity compared to the sample with conventional flat MQWs structure. In addition, the PL emission peak shows a blue shift from 452 (flat MQWs) to 446nm (NGS sample with a 200nm period), which may be explained by a partial strain release in MQWs that induces a lower piezoelectric field in the active layer.

Photo-induced and Thermal Annealing of Chalcogenide Films for Waveguide Fabrication

We describe the effect of light-induced annealing of As2S3 thin films and its impact on the performance of an optical waveguide. An as-deposited film was subjected to illumination with band-edge light before being used to fabricate sub- micron thick waveguides using photolithography and dry plasma etching. Studies of the film microstructure revealed a difference between the atomic bonds and linked phases between the as-deposited, the thermally-annealed, and the optically-annealed films. Although optical-annealing evolves the structure of the film in a similar way to thermal annealing (i.e., it causes polymerization of the glass network), it can drive the film much closer to bulk state in terms of refractive index and the numbers of wrong bonds. The waveguides showed, however, almost the same propagation losses to those from thermally-annealed material. Nonetheless our results indicate that optical-annealing provides some advantages over thermal annealing for waveguide fabrication.

Fabrication of 3D hexagonal bottle-like Si–SnO2 core–shell nanorod arrays as anode material in on chip micro-lithium-ion-batteries

Three-dimensional (3D) Si–SnO2 composite core–shell nanorod arrays were fabricated as the anode material in lithium ion micro-batteries by nanosphere lithography (NSL) combined with inductive coupled plasma (ICP) dry etching technology. The hexagonal bottle-like Si NR arrays in wafer scale with homogeneous morphology and good mechanical structure provide enough space to accommodate the volume expansion during Li ion insertion/de-insertion processes, while the additionally deposited SnO2 thin film was prepared to successfully improve the capacities and cycle performance by configuring the 3D Si–SnO2 NR composite electrode arrays. This fabrication method has the advantages of simplicity, large scale production, easy size and shape manipulations, low cost and Si-process compatibility. This work will facilitate the configuration of solid state micro-batteries for power supply in micro-electronic devices, such as MEMS devices or smart IC chips.

Enhanced Efficiency of GaAs Single-Junction Solar Cells with Inverted-Cone-Shaped Nanoholes Fabricated Using Anodic Aluminum Oxide Masks

The GaAs solar cells are grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD) and fabricated by photolithography, metal evaporation, annealing, and wet chemical etch processes. Anodized aluminum oxide (AAO) masks are prepared from an aluminum foil by a two-step anodization method. Inductively coupled plasma dry etching is used to etch and define the nanoarray structures on top of an InGaP window layer of the GaAs solar cells. The inverted-cone-shaped nanoholes with a surface diameter of about 50 nm are formed on the top surface of the solar cells after the AAO mask removal. Photovoltaic and optical characteristics of the GaAs solar cells with and without the nanohole arrays are investigated. The reflectance of the AAO nanopatterned samples is lower than that of the planar GaAs solar cell in the measured range. The short-circuit current density increased up to 11.63% and the conversion efficiency improved from 10.53 to 11.57% under 1-sun AM 1.5 G conditions by using the nanohole arrays. Dependence of the efficiency enhancement on the etching depth of the nanohole arrays is also investigated. These results show that the nanohole arrays fabricated with an AAO technique may be employed to improve the light absorption and, in turn, the conversion efficiency of the GaAs solar cell.

Surface Treatment for GaN Substrate -Comparison of Chemical Mechanical Polishing and Inductively Coupled Plasma Dry Etching -

Surface Treatment for GaN Substrate -Comparison of Chemical Mechanical Polishing and Inductively Coupled Plasma Dry Etching -

Light Output Enhancement of InGaN/GaN Light‐Emitting Diodes with Contrasting Indium Tin‐Oxide Nanopatterned Structures

Various nanopatterns on the transparent conducting indium tin oxide (ITO) layer are investigated to enhance the light extraction efficiency of the InGaN/GaN light‐emitting diodes (LEDs). Triangular, square, and circular nanohole patterns with the square and hexagonal lattices are fabricated on the ITO layer by an electron beam lithography and inductively coupled plasma dry etching processes. The circular hole pattern with a hexagonal geometry is found to be the most effective among the studied structures. Light output intensity measurements reveal that the circular hole nanopatterned ITO LEDs with a hexagonal lattice show up to 35.6% enhancement of output intensity compared to the sample without nanopatterns.

One-step sculpting of silicon microstructures from pillars to needles for water and oil repelling surfaces

Surfaces that repel both water and oil effectively (contact angles > 150°) are rare. Here we detail the microfabrication method of silicon surfaces with such properties. The method is based on careful tuning of the process conditions in a reactive etching protocol. We investigate the influence of SF6, O2 and CHF3 gases during the etching process using the same pitch of a photolithographic mask. Varying the loading conditions during etching, we optimized the conditions to fabricate homogeneous pedestal-like structures. The roughness of the microstructures could also effectively be controlled by tuning the dry plasma etching conditions. The wetting behavior of the resulting microstructures was evaluated in terms of the water and oil contact angles. Excitingly, the surfaces can be engineered from superhydrophobic to omniphobic by variation of the aforementioned predefined parameters.

Atomic layer deposition of aluminum-doped zinc oxide films for the light harvesting enhancement of a nanostructured silicon solar cell

Anodic-aluminum-oxide (AAO) template lithography and atomic layer deposition (ALD) antireflection coating techniques have often been applied for the fabrication of wide-angle antireflection structures on silicon solar cells. In this study, an AAO template was fabricated as a mask to block the high density plasma dry etching from the crystalline silicon to form nanostructures on the surface of the crystalline silicon wafer. Then, a 55-nm-thick aluminum-doped zinc oxide (AZO) film was deposited on the silicon nanostructures using the ALD method. The results show that the application of a nanostructured AZO film can decrease the average reflectivity of the crystalline silicon to 0.83% in the wavelength range from 400 to 850 nm for an incident angle of 8°. The conversion efficiency of the nanostructured silicon solar cell can be enhanced from 6.93% to 8.37%.

Micropatterning PEDOT:PSS layers

PEDOT:PSS is a conductive polymer that is used as electrodes in organic electronic devices, but also in neuronal probes and implantable devices. This material can also be used for building deformable electrodes in soft substrates for several sensing applications. However, this material being sensitive to several chemicals and moisture it is difficult to pattern microstructures using standard lithography techniques. This paper will review and show some techniques developed for patterning PEDOT:PSS thin films using both soft lithography, such as microcontact printing and shadow masking, and conventional lithography techniques. In addition of this review we present a new lithography technique using silicon nitride protection layer and an analysis and comparison of ICP RIE dry plasma etch rates of PEDOT:PSS with different gases.

$\hbox{MoS}_{2}$ Nanoribbon Transistors: Transition From Depletion Mode to Enhancement Mode by Channel-Width Trimming

We study the channel width scaling of back-gated MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> metal-oxide-semiconductor field-effect transistors from 2 μm down to 60 nm. We reveal that the channel conductance scales linearly with channel width, indicating no evident edge damage for MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanoribbons with widths down to 60 nm as defined by plasma dry etching. However, these transistors show a strong positive threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) shift with narrow channel widths of less than 200 nm. Our results also show that transistors with thinner channel thicknesses have larger <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shifts associated with width scaling. Devices fabricated on a 6-nm-thick MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> crystal underwent the transition from depletion mode to enhancement mode.

Direct SiGe BFFT Patterning by Dry Plasma Etching

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Gas Sensors Based on One Dimensional Nanostructured Metal-Oxides: A Review

Recently one dimensional (1-D) nanostructured metal-oxides have attracted much attention because of their potential applications in gas sensors. 1-D nanostructured metal-oxides provide high surface to volume ratio, while maintaining good chemical and thermal stabilities with minimal power consumption and low weight. In recent years, various processing routes have been developed for the synthesis of 1-D nanostructured metal-oxides such as hydrothermal, ultrasonic irradiation, electrospinning, anodization, sol-gel, molten-salt, carbothermal reduction, solid-state chemical reaction, thermal evaporation, vapor-phase transport, aerosol, RF sputtering, molecular beam epitaxy, chemical vapor deposition, gas-phase assisted nanocarving, UV lithography and dry plasma etching. A variety of sensor fabrication processing routes have also been developed. Depending on the materials, morphology and fabrication process the performance of the sensor towards a specific gas shows a varying degree of success. This article reviews and evaluates the performance of 1-D nanostructured metal-oxide gas sensors based on ZnO, SnO2, TiO2, In2O3, WOx, AgVO3, CdO, MoO3, CuO, TeO2 and Fe2O3. Advantages and disadvantages of each sensor are summarized, along with the associated sensing mechanism. Finally, the article concludes with some future directions of research.

Comparison of Two Types of Recessed-Gate Normally-Off AlGaN/GaN Heterostructure Field Effect Transistors

In this report, two types of normally-off AlGaN/GaN heterostructure field effect transistors (HFETs) with recessed-gate structure have been fabricated by using common technique of induced coupled plasma (ICP) dry etching and a novel technique of selective area growth (SAG), respectively. The devices fabricated by SAG (SAG-HFET) showed better performance than that of ICP-HFETs with larger maximum drain current of 300 mA/mm, positive threshold voltage of 0.4 V, and lower pinch off channel leakage current (2.17×10-3 mA/mm). The analysis indicates that such obvious difference originated from the different AlGaN quality of the gate region under the Schottky contact, in which the damage to the gate region stemmed from dry etching can be avoided by the SAG technique so that the forming of higher quality Schottky contact can be guaranteed. These results indicate that SAG technique is a promising method for fabricating the normally-off GaN based HFETs.