Pipelined Multiplier Research Articles

Pipelined carry look-ahead adder

A pipelined carry look-ahead adder is described which is particularly suitable for use with a pipelined parallel multiplier, but would also be useful for other pipelined systems. The adder is compared with a pipelined ripple-carry adder having a triangular structure and the nonpipelined form of the carry look-ahead adder and is shown to possess the advantages of small stage delay and short flush time.

A Pipelined 330-MHz Multiplier

An 8X8-bit multiplier test circuit developed in a 1-/spl mu/m NMOS technology is described. To achieve a high throughput rate, extensive pipelining is used in a semi-systolic fashion. It is shown that this saves area and allows for shorter cycle times compared to a pure systolic array. Problems with widely distributed lines (broadcasting) are avoided by a novel carry-save-adder cell. The data inputs and outputs are ECL compatible. The circuit contains 5480 MOSFET's in an active area of 0.6 mm/sup 2/. Effective channel lengths of 0.9 and 1.1 /spl mu/m are utilized for the enhancement and depletion transistors with a gate oxide thickness of 12.5 nm. The power dissipation is 1.5 W at a supply voltage of 3 V. The test chip operates up to a clock frequency of 330 MHz at room temperature and up to 600 MHz with liquid nitrogen cooling. This demonstrates the applicability of large-scale integrated MOS circuits in a frequency range of several hundred megahertz.

A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

It is shown how distributed arithmetic techniques can be applied in parallel-data arithmetic computations to achieve highly regular and efficient VLSI structures on silicon. Two individual arithmetic processor chips are described as examples of the technique. The chips described, which are intended primarily for computation of the FFT butterfly, each contain the functional equivalence of two parallel pipelined multipliers. The first chip is an 8-bit prototype device which has been designed and fabricated on a standard 5-/spl mu/m silicon-gate n-channel MOS process. The second chip is a 16-bit CMOS-SOS design which uses a modified architecture to achieve higher clocking rates and improved versatility in systems use.

Transmultiplexers: Current Trends

With the increasing introduction of digital communication equipment within the existing analogue communication network and the consequent requirement of interconnecting the two, the need for conversion or translation between TDM/FDM and vice-versa is growing.Transmultiplexing (TMX) or the process of translation between FDM and TDM offers interesting application possibilities. The paper defines the Transmultiplex problem, describes the basic methods of Transmultiplexing and the details of design considerations of a 120-channeI TMX system.The paper concludes with a review of the present trends in TMX, like the use of multistage structure of digital filters, development of LSI circuits with single chip arithmetic processor with multiplier capability, the NEC made VLSI (16 bit pipe-line multiplier (MPL)) which can realise any digital signal processor etc.

Implementation of signal processing functions using 1-bit systolic arrays

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined briefly.

Single-chip per channel codec with filters utilizing Δ-Σ modulation

A single-chip per channel codec with filters, fabricated using a single poly-Si NMOS technology, is discussed. In the encoder, the analog signal is converted to a 2.048 M samples/s digital signal by a /spl Delta/-/spl Sigma/ modulator. Filtering necessary for the sampling rate 8 k sample/s and compression by the /spl mu/255 law are performed digitally. In the decoder, the 8 k samples/s PCM is successively resampled and converted into the 2.048 M samples/s /spl Delta/-/spl Sigma/ signal, which is then decoded by a /spl Delta/-/spl Sigma/ demodulator. All the high-frequency images, which appear around multiples of 8 kHz, are removed by digital filters. The chip has continuous-signal antialiasing and smoothing filters for the 2.048 Samples/s sampling rate. It also has reference voltage generators for /spl Delta/-/spl Sigma/ modulation/demodulation. Some of the observed characteristics are given. The NMOS /spl Delta/-/spl Sigma/ modulator requires only two on-chip matched capacitors as precision components, and does not require a linear amplifier. A deliberate quantization step imbalance is introduced to allow a low sampling rate. The main band limiting for the 8 k samples/s is done by the recursive filter. This is realized with the serial-parallel pipeline multiplier (SPPM) in four-phase logic. The whole system is integrated on a 296 mil/spl times/342 mil chip.

120-Channel Transmultiplexer Design and Performance

A 120-channel transmultiplexer has been developed which interfaces two FDM basic supergroup signals (2 x 60 channels) directly to the digital time division switch or digital transmission systems. The equiplnent exploits a block processing digital SSB-FDM multiplex/demultiplex scheme, and has been built using newly developed high-speed CMOS pipeline multipliers and variable length shift registers. System design considerations and hardware implementation techniques are described in detail as well as the measured performance.

Cellular two's complement serial—pipeline multipliers

Serial two's complement pipeline multipliers are the basic module in the serial arithmetic implementation of digital signal processing algorithms. These multipliers accept the data serially in two's complement notation and generate a serial output product in two's complement notation as well. The designs, however, presented up to now lack in modularity; in addition, they have the problem of the internal overflow. In this paper a new two's complement multiplication algorithm is worked out, that allows cellular implementation of serial-pipeline multipliers and does not limit the dynamic range of the data input. In addition, by using the proposed cell, useful functions for digital signal processing can be performed. Methods are proposed for overflow detection, and comparison is made with previously proposed realizations.

The TMC0280 speech synthesizer (Part I)

The TMC0280 is a one‐chip speech synthesizer based on the technique of linear predictive coding. The considerations leading to the choice of LPC‐10 for a high quality, low cost speech synthesizer are outlined and the resulting synthesis algorithm is discussed. The key computational innovations introduced in this chip include a pipelined multiplier and adder. Combined with the proper computational ordering, this allows a monolithic PMOS implementation of the all‐pole lattice filter. The input to the 0280 is a coded bit stream representing the parameters of energy, pitch, and reflection coefficients. Using variable data length frames, the chip is capable of generating good quality speech from a data rate of 1200 bits per second. The synthesizer operates at up to a 10 kHz sample rate. Further capabilities of the chip are discussed and a demonstration of the speech quality will be presented. [Part II of this paper will be given by Larry Brantingham and concerns the hardware implementation.]

A modular, high-speed serial pipeline multiplier for digital signal processing

Describes the design and implementation of a 44 Mbit/s serial pipeline multiplier that exploits an efficient algorithm with a novel circuit architecture. The multiplier, intended for use with signed-magnitude coefficients and two's complement data of arbitrary length, produces products automatically rounded and truncated to the same length as incoming data. The circuit's design focuses on the bit-cell, a unit of circuitry associated with one bit of the coefficient word, from which multipliers of arbitrary complexity may be constructed. A practical realization of this multiplier contains four bit-cells, each of which dissipates 20 mW, as well as all associated data, coefficient, and control registers necessary for its operation. The total power dissipation for the chip is 140 mW. The physical implementation of the multiplier employs buried-collector bipolar devices and two-level aluminum metallization to obtain a compact chip 120 mil/SUP 2/. Descriptions of the circuit's arithmetic architecture, design, performance, and use are given in detail.

Design and Performance of a Digital Multifrequency Receiver

An experimental multifrequency receiver for recognition of digitally encoded multifrequency signaling was designed, constructed and tested. The receiver is based on a quadrature detection technique that consists of digital demodulation followed by second-order, lowpass digital filtering. The post filtering processing produces an estimate of the amplitude of each of the six multifrequency tones and provides suitable information for thresholding and timing measurements. The receiver performs correctly even when subjected to severe environmental conditions including an analog signal range of 23 dB, 10 ms signal interruptions ('hits') and 20 ms signal spacings. The receiver's operation demonstrates the robustness of the digital signal processing techniques employed. The design of the receiver exploits the use of subsampling techniques to increase the efficiency of the hardware through greater multiplexing. When using subsampling, 128 multifrequency receivers with 16-bit words are realized with 6.5 dual-in-line packages per receiver; commercial TTL logic circuits, a 4-bit serial-parallel pipeline multiplier circuit, serial data and a 16.384 MHz clock are assumed.

A low-power, bipolar, two's complement serial pipeline multiplier chip

A 4-bit, general-purpose, two's complement serial pipeline multiplier chip has been designed and fabricated in the bipolar GIMIC-O process. The chip can provide the following functions in 24-pin dual-in-line packages: (1) two's complement/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (2) sign magnitude/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (3) 5-bit dynamically programmable adder/subtractor, (4) 2/SUP -K/ scaler; (5) overflow corrector. Packages can be cascaded to provide functions of length greater than 4 bits. Nonsaturating circuit techniques, emitter function logic combined with current-steering trees, are effectively utilized to make high-performance, low-power circuits using a simple bipolar technology. The multiplier circuitry is compatible at inputs and outputs with standard emitter coupled logic and uses a standard -5.2/spl plusmn/10 percent power supply. Fully programmable multiplication at clock rates greater than 20 MHz is achieved with a power consumption of 37.5 mW/bit.

Two's Complement Pipeline Multipliers

Digital filters and signal processors when realized in hardware often use serial transfer of data. Multipliers which are capable of accepting variable coefficients and data in sign and magnitude notation and producing serial products of the same length as the input data word have been known for some time. This concise paper addresses the design of multipliers capable of accepting data in 2's complement notation, or both data and coefficients in 2's complement notation. It also considers multiplier recoding techniques, such as the Booth algorithm. Specialized (fixed coefficient) multiplier designs are considered briefly. Finally, multiplier rounding and overflow characteristics are discussed, and a rough comparison is made between the complexity of the various designs.