Abstract
Serial two's complement pipeline multipliers are the basic module in the serial arithmetic implementation of digital signal processing algorithms. These multipliers accept the data serially in two's complement notation and generate a serial output product in two's complement notation as well. The designs, however, presented up to now lack in modularity; in addition, they have the problem of the internal overflow. In this paper a new two's complement multiplication algorithm is worked out, that allows cellular implementation of serial-pipeline multipliers and does not limit the dynamic range of the data input. In addition, by using the proposed cell, useful functions for digital signal processing can be performed. Methods are proposed for overflow detection, and comparison is made with previously proposed realizations.
Published Version
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