The FFT butterfly operation in 4 processor cycles on a 24 bit fixed-point DSP with a pipelined multiplier

M Grajcar,B Sick

doi:10.1109/icassp.1997.599842

The FFT butterfly operation in 4 processor cycles on a 24 bit fixed-point DSP with a pipelined multiplier

M Grajcar, B Sick

https://doi.org/10.1109/icassp.1997.599842

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Publication Date: Apr 21, 1997

Citations: 3

Affiliation: University of Passau

#Fixed-point Digital Signal Processors #Digital Signal Processors + Show 8 more

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Abstract

Most of the existing Digital Signal Processors (DSPs) are optimized for a fast and efficient computation of the Fast Fourier Transform (FFT). However, there are only two floating-point DSPs available, which perform the butterfly operation of a FFT in 4 processor cycles, but no fixed-point DSP is designed that way. The new 24 bit fixed-point DSP DAISY, which is able to execute the butterfly in 4 cycles even using a two-stage pipelined multiplier, is described in this paper. With this pipelined multiplication it is possible to reduce the processor cycle time significantly.

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