Pipelined Multiplier Research Articles

High performance computing through SoC coprocessors

In this paper we describe DPFPA (Double Precision Floating Point Accelerator), a FPGA-based coprocessor interfaced to the CPU through standard bus connections; it is conceived to accelerate double precision floating point operations, featuring two double precision floating point units, a pipelined adder and a pipelined multiplier with a suitable number of stages. We tested its performance by implementing a Montecarlo-Metropolis simulation of a dipolar system, using a proper software development environment designed and realized in our laboratory. DPFPA can provide a speed-up equal to 4, with respect last generation PC, showing also a good scalability in terms of clock frequency, memory capability and number of computing units.

Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers

In this paper, we propose a pipelined reconfigurable fixed-width Baugh-Wooley multiplier design framework that provides four configuration modes (CMs): n × n fixed-width multiplier, two n/2 × n/2 fixed-width multipliers, n/2 × n/2 full-precision multiplier, and two n/A × n/A full-precision multipliers. Furthermore, low-power schemes including gated clock and zero input techniques are employed to achieve the power-efficient pipelined reconfigurable design. The presented power-efficient pipelined reconfigurable fixed-width multiplier design not only generates a family of widely used multipliers but also leads to 10.59, 21.7, 28.84, and 31.58 percent power saving, on average, for n = 8,16,24, and 32, respectively, compared with that of the pipelined reconfigurable fixed-width multiplier without using the low-power schemes. On the other hand, compared with non-reconfigurable pipelined multiplier, we can save 0.81, 12.46, 17.93, and 23.2 percent power consumption, respectively, for n = 8,16,24, and 32.

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. In the TSMC 0.25-mum CMOS technology, we implemented 1024 proposed energy recovery clocked flip-flops through an H-tree clock network driven by a resonant clock-generator to generate a sinusoidal clock. Simulation results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops. Using a sinusoidal clock signal for energy recovery prevents application of existing clock gating solutions. In this paper, we also propose clock gating solutions for energy recovery clocking. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000times in the idle mode with negligible power and delay overhead in the active mode. Finally, a test chip containing two pipelined multipliers one designed with conventional square wave clocked flip-flops and the other one with the proposed energy recovery clocked flip-flops is fabricated and measured. Based on measurement results, the energy recovery clocking scheme and flip-flops show a power reduction of 71% on the clock-tree and 39% on flip-flops, resulting in an overall power savings of 25% for the multiplier chip.

Performance evaluation of multipliers in reconfigurable hardware

Hardware multiplier is a critical element in many computing intensive sub-systems that are implemented in Field Programmable Gate Arrays (FPGAs). In this study, performance comparison between several different types of array-based unsigned 8-bit multipliers (both combinational and pipelined) for two types of FPGAs (XC4005XLPC84-3C and XC3S1000FT256-4C Spartan 3) in terms of resource utilization and critical path delays was carried out. For combinational multipliers, the embedded multiplier in the high density Spartan 3 FPGA has the lowest critical path delay. MUX-based Carry Save Array (CSA) multiplier when implemented in the low density XC4005 FPGA, utilized 24% less resources and resulted is 42% improvement in the latency than the standard multiplier available in the hardware description language (VHDL) library. For pipelined multipliers, single stage pipelined multiplier of the same architecture, for the same chip, utilized 18% more resources but produced a 84% improvement in the latency. Thus, to obtain the optimum performance of FPGA hardware in high speed applications, MUX-based pipelined CSA multipliers are recommended. Keywords: FPGA, Multiplier hardware architecture, reconfigurable computing, VHDL doi:10.4038/jnsfsr.v36i3.160 Journal of the National Science Foundation of Sri Lanka 36 (3) 235-237

Designing an ultra-high-speed multiply-accumulate structure

In this article, an ultra-high-speed multiply-accumulate (MAC) structure is proposed. This fused MAC block uses low-voltage-swing (LVS) technique in the utilized carry-save adders and the final adder to improve its speed. Carry-save adders and the final adder are implemented with pass-transistor-based Manchester-carry-chain logic. Sense amplifiers are used in the output nodes to amplify the LVS signals to the standard levels of zero and one. With this technique, we achieved the outstanding clock frequency of 15GHz for a five-stage pipelined MAC, which is 87.5% higher than the highest speed achieved for a pipelined multiplier in 65nm technology and above, with the power consumption of 25mW/GHz in 1.2V voltage supply.

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultrathin-body fully depleted silicon-on-insulator transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed, and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier. The variability analysis on both dc and ac characteristics indicates that the benefits of selective footprint scaling are not degraded by device variation

Energy-aware design for multi-rail encoding using NCL

A novel technique named Signal Bypassing and Zero Insertion to design energy-aware asynchronous circuits in multi-rail encoding logic is developed. Several examples including pipeline components, multiplier, and counter are designed and simulated. The proposed technique has advantages in energy saving and delay reduction as well.

Optimization techniques for FPGA-based wave-pipelined DSP blocks

In this paper, techniques for efficient implementation of field-programmable gate-array (FPGA)-based wave-pipelined (WP) multipliers, accumulators, and filters are presented. A comparison of the performance of WP and pipelined systems has been made. Major contributions of this paper are development of an on-chip clock generation scheme which permits finer tuning of the frequency, a synthesis technique that reduces the area and latency by 25%, a placement utility that results in 10%-40% increase in speed and proposal of an interleaving scheme for filters that reduces the number of multipliers required by 50%. WP multipliers of size 2 /spl times/ 6 and the filters using them are found to be 11% faster and require lower power than those using pipelined multipliers. Filters with higher order WP multipliers also operate with lower power at the cost of speed. The delay-register products of such filters are found to be about 60% lower than those using the pipelined multipliers. The paper also outlines applications of these techniques for the Spartan II FPGAs and a self-tuning scheme for optimizing the speed.

Scalable Normal Basis Arithmetic Unit for Elliptic Curve Cryptography

The design of a scalable arithmetic unit for operations over elements of GF(2m) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in a single arithmetic unit. We discuss optimum design of the shifter with respect to the inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA.We present implementation data for various digit widths which exhibit a time minimum for digit width D = 15.

Testing high-performance pipelined circuits with slow-speed testers

This article presents a methodology for testing high-performance pipelined circuits with slow-speed testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. The technique adds no extra hardware in the data path of the pipeline and therefore has virtually no performance penalty. A clock timing circuit capable of achieving a timing resolution of 50 ps in 0.18 μm CMOS technology is presented. The design provides the ability to test the clock timing circuit itself. The effectiveness of the technique is demonstrated using a 16-bit pipelined multiplier as a test vehicle. Simulations show that we are able to detect delay faults as small as 50 ps at an input clock frequency of 100 MHz.

LOW COST APPROXIMATE ADDER SUBTRACTOR FOR FIR FILTER

The cost of the FIR filter depends on the cost of its components that are classified into three types namely buffer, multiplier and adder/subtractor.The adder/subtractor cover the most FIF. rilter components and any reduction in its cost means high reduction in the total cost of FIR filter. tn addition, FIR filters with pipeline multiplier the speed of FIR depends on the speed of adder/subtractor and any improvement in speed will result to increasing in the total speed of such filter.This paper shows a proposed method to increase the speed and reduce the cost of the adder/subtractor by neglecting the rotated carry output. This method reduces the accuracy of FIRfilter, in other words it adds small noise to the output of the filter, but the level of this noise is inversely proportional with the number of bits in data bus of FIR filter. Therefore this method will be used with midum noise output filters or with wide data bus (12-bits or more) FIR filter.

Implementation of phase-mode arithmetic elements for parallel signal processing

We report the preliminary designs and the experimental results of high-speed digital processing elements based on phase-mode logic circuits. The core cell of these elements is a bit-serial adder cell consisting of the ICF gate which is the basic gate of phase-mode logic. Our main target is the application of the logic circuits to Digital Signal Processing. The basic arithmetic operations of DSP are a multiplication and an addition. Basic concept of the phase-mode pipelined parallel multiplier has been proposed previously. We design a 2 /spl times/ 2 AND array block and a 2-bit ripple-carry adder for the primitive parallel pipelined multiplier and also a 2-bit subtractor with a pipelined structure. These processing elements have been fabricated using NEC standard 2.5 kA/cm/sup 2/ Nb/AlOx/Nb process. The low-speed test results of these elements show correct operations. Numerical simulations show that a carry save adder (a 2-bit ripple carry adder) can operate over 10 GHz. We also discuss the prospects of large-scale SFQ DSP based on Nb junction technology.

Design and demonstration of SFQ pipelined multiplier

We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSA's). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of /spl plusmn/5.5%.

Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers

An embedded test pattern generator scheme for large-operand (unlimited bit length) multiplier and divider is presented by employing a simple digital circuit. This scheme is based on the generation of cyclic code polynomials from a characterized polynomials generator G(X) and incorporated with Modified-Booth algorithm. Due to the advantages of the former, the hardware complexity is simple, and moreover, the multiplier and divider can share the same hardware with a small change of control lines. Due to the advantages of latter's schemes, the numbers of “sub/add” operations are reduced to one half of the multiplicand for the result of final product. Therefore, the proposed pipelined multipliers permit very high throughput for arbitrary value of digit size. Only full adders/subtractors and shift registers are used in the proposed multiplier and divider hardware. The input data of the multiplier/divider can be processed in parallel or in pipelined without considering carry/borrow delays during the operations. The speed of computation has therefore been greatly improved by approximately a factor of 2. Since most parts of the components can be used for both the multiplier and divider, with full adders replaced by subtractors for switching from a multiplier to a divider, the structure is therefore tremendously reduced. In addition, these function units are involved with cyclic code generators, so that they can be used as a built-in self-test (BIST).

Phase-mode pipelined parallel multiplier

We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 10 GHz.

Interlaced diagonal-wise pipelined serial multiplier

A new two's complement serial multiplier based on a pipelined diagonal-wise interlaced structure is presented. Two N/spl times/M multiplications are processed simultaneously, which is particularly useful for a high-throughput area-efficient complex number multiplier. Using the proposed scheme, an 8/spl times/8 bit complex multiplier prototype was realised in 0.2 /spl mu/m standard cell CMOS technology with 1.6 Kgates complexity for a maximum operating frequency of 550 MHz.

Improving Goldschmidt division, square root, and square root reciprocal

The aim of this paper is to accelerate division, square root, and square root reciprocal computations when the Goldschmidt method is used on a pipelined multiplier. This is done by replacing the last iteration by the addition of a correcting term that can be looked up during the early iterations. We describe several variants of the Goldschmidt algorithm, assuming 4-cycle pipelined multiplier, and discuss obtained number of cycles and error achieved. Extensions to other than 4-cycle multipliers are given. If we call G/sub m/ the Goldschmidt algorithm with m iterations, our variants allow us to reach an accuracy that is between that of G/sub 3/ and that of G/sub 4/, with a number of cycle equal to that of G/sub 3/.

Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops

This paper describes the design of a low-power pipelined multiplier. It is illustrated in this paper that the power consumption of the clocking system cannot be overlooked and the design of the storage element is the key to low power. A new pulse-triggered true single-phase clocking (TSPC) flip-flop (PTTFF) is proposed for this purpose in this design. The PTTFF features true single-phase clocking, simple structure, and high performance. One PTTFF comprises only five transistors with only one controlled by the clock. Using the PTTFF together with the 14-transistor pseudo-NMOS full adder, an 8-b/spl times/8-b pipelined multiplier has been designed and implemented, employing a 0.6-/spl mu/m CMOS process. When the multiplier operates at the operating frequency of 300 MHz with VDD equal to 3.3 V, it dissipates only 53% of the power of the multiplier designed with nine-transistor TSPC flip-flops under the same operating conditions. When the supply voltage for the core array is reduced to 2.5 V, the multiplier can still work up to 300 MHz with only 47% of the power of the multiplier designed using the S and D full adders and C/sup 2/MOS latches with VDD equal to 3.3 V. The chip has been fabricated, and the measured power is 52.4 mW when operated at 300 MHz and 3.3 V.

Constant Number Serial Pipeline Multipliers

The pipeline form of the serial/parallel multiplier for constant numbers, which operates without insertion of zero words between successive data, is presented. The constant number is in Canonical Signed Digit (CSD) form and the other factor in two's complement form. The CSD form was chosen because it yields significant hardware reduction. Also, for the above data forms the Lyon's serial pipeline multiplier is examined. For these designs, a special algorithm for the multiplication of two's complement numbers with constant numbers in CSD representation was developed. The proposed serial pipeline multipliers are compared with the existing schemes from the point of hardware complexity.

A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V dd 2, decreasing the supply voltage yields a large reduction in power consumption. The main design objectives for these circuits are glitch-free operation and low power consumption at low supply voltage. The proposed D-FF circuit has been compared with previously known circuits and has been shown to provide superior performance. All circuits in this paper have been simulated using HSPICE with a 0.4-μm CMOS technology at a 2-V supply voltage. An analysis of a serial pipeline multiplier design establishes the superiority of the proposed circuit in that application.