Interlaced diagonal-wise pipelined serial multiplier

Abstract

A new two's complement serial multiplier based on a pipelined diagonal-wise interlaced structure is presented. Two N/spl times/M multiplications are processed simultaneously, which is particularly useful for a high-throughput area-efficient complex number multiplier. Using the proposed scheme, an 8/spl times/8 bit complex multiplier prototype was realised in 0.2 /spl mu/m standard cell CMOS technology with 1.6 Kgates complexity for a maximum operating frequency of 550 MHz.