Complementary HFET 32-bit serial multiplier

Abstract

A 32-bit serial integer multiplier was designed to investigate the yield and performance of complementary HFET technology. An average wafer yield of 20% was obtained. A power dissipation of 3 mW (about 1 mu W per equivalent gate) at 5 MHz operation was demonstrated, which is among the lowest reported for any GaAs logic circuit. The maximum operating frequency was 500 MHz with power dissipation of 2.5 W at a supply voltage of 2.36 V. Lower threshold voltages were obtained with implanted n-type transistors on non-delta doped wafers. This resulted in up to a 50% reduction in the static power dissipation at the same operating frequency. >