Pipelined Circuit Research Articles

An Edge Neuromorphic Hardware With Fast On-Chip Error-Triggered Learning on Compressive Sensed Spikes

This brief proposes an edge neuromorphic hardware design for real-time energy-efficient applications. It is capable of fast on-chip learning on compressive sensed spikes utilizing an error-triggered learning mechanism. Our hardware architecture consists of two event-driven arrays of parallel computing cores, and adopts fine-grained pipeline circuits to boost processing speed. The architecture has good scalability and provides a flexible trade-off among processing speed, recognition accuracy and resource cost. Our design was prototyped on the very-low-cost Xilinx Zynq-7010 FPGA chip on a Zybo platform. The FPGA prototype realized a high processing speed of 4843 and 4931 frames/s with a high energy efficiency of 31.39 lJ/image and 30.83 lJ/image on the MNIST image set during training and inference, respectively. The prototype reached comparably high on-chip learning accuracies across a serial of datasets including both static images as well as spike event streams, e.g., 95.02% on the MNIST images and 84.46% on the N-MNIST streams.

Design of Montgomery Multiplier – RSA Algorithm

In cryptography, during the process of encryption, we use multiplication modulo architectures (2^n- 1) and (2^n+ 1) are proposed that enable the implementation of very efficient combinational and pipelined circuits for modular arithmetic. This project is an improvisation of existing modulo multiplier architectures for higher speed and regularity. We use the Montgomery multiplier in this project for the RSA algorithm. Hence, the IDEA block cipher is represented as a high-performance modulo multiplier adder. The circuits that arise are compared qualitatively and quantitatively for the RSA algorithm.

Investigation of asynchronous pipeline circuits based on bundled-data encoding: Implementation styles, behavioral modeling, and timing analysis

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance. In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.

A low-power twiddle factor addressing architecture for split-radix FFT processor

The split-radix fast Fourier transform (SRFFT) is attractive for low-power FFT processors as it has the lowest numbers of multiplication operations among all FFT algorithms. FFT algorithms differ from one another by the location of the twiddle factor. The irregular locations of the twiddle factors in the SRFFT lead to complex address generators for the memory containing the twiddle factors. This paper proposes a novel twiddle factor addressing architecture for the split-radix FFT processor, which can effectively reduce its power consumption. This is then used to design a simple memory address generator and a low-power pipelined SRFFT. The proposed algorithm is used to implement a 1024-point pipelined circuit. Post-layout simulation shows that the proposed 1024-point design achieves over 24% and 14.7% lower power consumption for the multiplications and ROM, respectively, compared to a traditional radix-2 single delay feedback (SDF) FFT architecture.

ON THE FORMATION OF DYNAMIC PROPERTIES OF PNEUMATIC AND HYDROMECHANICAL SYSTEMS

The article presents a brief analysis of the results of the work of the scientific school of the Academician of the Russian Academy of Sciences V.P. Shorin on the creation of methods and means for eliminating oscillations in pipeline chains of pneumatic and hydraulic systems. The principles of construction and possible structures of dampers for forced vibrations of the working medium, as well as criteria and methods for assessing the effectiveness of the dampers are stated. The possibility of using vibration dampers as correcting devices to ensure the stability of hydromechanical control systems and equalize the frequency characteristics of measuring pipeline circuits is shown.

Efficient Pipelined Circuits for Histogram-based Tone Mapping of Nonlinear CMOS Image Sensors

Abstract Tone mapping is extensively researched to address the issue of displaying high dynamic range (DR) scenes on low DR displays. Even though several tone-mapping operators (TMOs) exist, not all are designed for hard real time. The operator has to be capable of scaling up the spatial resolution without compromising the frame rate. The implementation of a TMO should also be simple enough to embed in low-cost platforms for imaging systems. A computationally efficient, and well accepted, class of TMOs are global ones based on histograms. This work presents a method to implement TMOs that use histograms. This method is suitable for low-cost field-programmable gate arrays (FPGAs), using simple components such as adders, multipliers, and random access memories, and is particularly suited for a nonlinear CMOS image sensor (CIS) operating continuously in hard real time. The authors develop a fixed-point design, validated in bit-true fashion using Xilinx and Altera tools, from a background algorithm implemented using Matlab. Our generic design uses pipelined circuits and operates with low latency. The use of a hardware description language to model our circuits guarantees portability and modularity. Moreover, the complete TMO is generated from design parameters and a design template. The architecture is robust and scales well from kilopixel to megapixel formats. The circuits achieve 30 frames per second, at high definition resolutions, while occupying only a small fraction of the available logic elements in a low-cost FPGA device.

A Review on Mechanisms and Testing of Wear in Slurry Pumps, Pipeline Circuits, and Hydraulic Turbines

AbstractThis paper presents an overview about particulate wear that occurs in various components of slurry pumps, pipeline systems, and hydraulic turbines due to the mechanical action caused by the flow of solid–liquid mixtures. Three most common wear problems, namely, erosion, erosion–corrosion, and abrasion occur in different industries like thermal and hydro power plants, mining, chemical, and marine industries. Therefore, the efficiency of these industries and power plants highly depends on the wear damages. So, it becomes necessary to govern the wear phenomenon. In this paper, the various properties of particles and target are discussed on which the particulate wear depends. Present overview explains the experimental methods of measuring the particulate wear at in situ and ex situ conditions by using the different types of testers, rigs, and pilot plant test loops. Moreover, the empirical and analytical correlations or models for the prediction of particulate wear in pumps, piping circuits, and hydraulic turbines are also discussed in present literature review. By studying the all possible advantages and disadvantages, the gaps in knowledge of wear prediction methods and models are highlighted. At the end, a “think-model” for the prediction as well as reduction of wear in the various components is presented on the basis of different experimental and computational fluid dynamics (CFD) based simulation work. Further investigations can be carried out to develop the more accurate and flexible models that can be used to predict the particulate wear in a wide range of applications.

Mathematical modelling of pipelines, including equipment, levelling sharp changes in fluid pressure

The article deals with the issues related to the modelling of unsteady fluid flow in short and long pipelines, including various equipment: pumping stations (equipped with cen-trifugal or piston pumps), valves of different operating principle, pressure stabilizers, etc. Pres-sure stabilizers (especially in short pipelines) are able to protect the pipeline from sudden pres-sure surges. This is important not only in terms of the strength of the pipeline system, but also in short pipeline circuits for a uniform flow of liquid fuel supply. As a mathematical tool for numerical solution of differential equations of quasi-hyperbolic type, the method of character-istics is applied, which allows to consider the problems that develop over time. The program is written in C++ with graphical interpretation in Maple.

Oral group medication in pig production: characterising medicated feed and drinking water systems.

Despite common use of oral group medication in pig rearing, the homogeneity, stability and carry-over of frequently used medicinal products in feed and drinking water are largely unknown. Therefore, a field study was performed on 52 Belgian pig farms, characterising preparation and administration of medicinal products via these systems, and farmers' user experiences with medicated feed and medicated drinking water. The study showed that medicated drinking water is more commonly used than medicated feed, since 90.4 per cent of the farms sometimes use medicated drinking water and 69.2 per cent of the farms sometimes use medicated feed. The drinking water quality is evaluated at least once a year on only 30.7 per cent of the farms. Separate pipelines for medicated and non-medicated circuits were not present in any of the farms using medicated feed and in 27.7 per cent of the farms using medicated drinking water. With drinking water medication, 63.5 per cent of the farmers reported encountering practical problems, often related to solubility issues and precipitation of the active compounds. In contrast, medicated feed is bought ready-to-use from the feed manufacturer in 68.2 per cent of the cases, thus reducing the number of practical problems experienced by the farmer. This study shows room for improvement of oral group treatment, developing appropriate pharmaceutical formulations for drinking water medication, quality control of drinking water, using separate pipeline circuits, and cleaning and disinfecting protocols.

An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network

Deep neural networks (DNNs) are effective machine learning models to solve a large class of recognition problems, including the classification of nonlinearly separable patterns. The training of DNNs is, however, particularly difficult due to the large size and high energy consumption of the networks. Recently, stochastic computation (SC) has been considered to implement DNNs to reduce the hardware cost. However, it requires a large number of random number generators (RNGs) and long stochastic sequences that lower the energy efficiency of the network. To overcome these limitations, we propose the design of an energy-efficient deep belief network (DBN) with online learning capacity based on stochastic computation. In the SC-DBN, a reconfigurable structure is utilized to implement the fast greedy learning algorithm and an adaptive moment estimation (ADAM) circuit is designed to improve the speed of the training process. An approximate SC activation unit (A-SCAU) is further designed to implement different types of activation functions in the neurons. The A-SCAU is immune to signal correlations, so the RNGs can be shared among all neurons in the same layer with no accuracy loss. The area and energy of the proposed design are less than 5.5% and 3.7% (or 29.3% and 33.3%) of a pipelined 32-bit floating-point (or an 8-bit fixed-point) implementation. The proposed SC-DBN design achieves a higher classification accuracy compared with the fixed-point implementation. The accuracy is in a range of 0.12% to 0.37% lower than the floating-point design with a significantly lower (or slightly higher) energy consumption than the pipelined (or non-pipelined) circuit for both online learning and inference processes.

A Deep Pipelined Implementation of Hyperspectral Target Detection Algorithm on FPGA Using HLS

Real-time target detection for hyperspectral images (HSI) has received considerable interest in recent years. However, owing to enormous data volume provided by HSI, detection algorithms are generally computationally complex, thus developing rapid processing techniques for target detection has encountered several challenging issues. It seems that using a deep pipelined structure can improve the detection speed, and implementing on field programmable gate arrays (FPGAs) can also achieve concurrent operations rather than run streams of sequential instruction. This paper presents a deep pipelined background statistics (DPBS) approach to optimizing and implementing a well-known subpixel target detection algorithm, called constrained energy minimization (CEM) on FPGA by using high-level synthesis (HLS). This approach offers significant benefits in terms of increasing data throughput and improving design efficiency. To overcome a drawback of HLS on implementing a task-level pipelined circuit that includes a feedback data path, a script based circuit design method is further developed to make connections between some of the modules created by HLS. Experimental results show that the proposed method can detect targets on a real-hyperspectral data set (HyMap Data) only in 0.15 s without compromising detection accuracy.

Efficient adders for assistive devices

The Body sensor network [IEEE 802.15] is a wireless communication network consisting of assistive devices which are of prime importance in medical applications. The delay critical and power hungry blocks in these assistive devices are designed so that they consume less power, have low latency and require a lesser area on chip. In this paper, we present a qualitative as well as a quantitative analysis of an asynchronous pipelined adder design with two latest computation completion sensing approaches based on Pseudo NMOS logic and other based on C-element. The Pseudo NMOS based completion sensing approach provides a maximum improvement of 76.92% in critical path delay at supply voltage of 1.2V and the maximum drop in power dissipation has been observed at a supply voltage of 1.1V which is 85.60% as compared to C-element based completion sensing approach. Even at low voltages such as 0.8V, there is a significant improvement in speed and power which is 75.64% and 74.79% respectively. Since the adder is the most widely used component in all present day assistive devices, this analysis acts as a pointer for the application of asynchronous pipelined circuits with efficient Pseudo NMOS based completion sensing approach in low voltage/low power rehabilitative devices.

Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits

As a type of side-channel attack, fault attacks on the hardware implementation of cryptographic algorithms has been widely studied, and has been successfully applied to a variety of ciphers. So far, many hardware countermeasures against fault attacks have been proposed. However, most of them are tailored to a specific cryptographic algorithm and cannot provide a comprehensive level of protection against all possible faults. In this paper, we present a novel, secure and generic framework based on the robustness of null convention logic pipelines and dual-rail encoded systems, which is resistant to fault attacks at the circuit level by implementing technologies such as rail synchronization, maximum delay matching, error-detecting monitors, and self-feedback mechanisms. Both the theoretical analysis and simulation results show that all faults at the output of computational blocks can be fully detected and corrected. The new framework gives us the ability to detect and correct the faults induced in the register.

Continuous‐flow variable‐length memoryless linear regression architecture

A pipelined circuit to calculate linear regression is presented. The proposed circuit has the advantages that it can process a continuous flow of data, it does not need memory to store the input samples and supports variable length that can be reconfigured in run time. The circuit is efficient in area, as it consists of a small number of adders, multipliers and dividers. These features make it very suitable for real-time applications, as well as for calculating the linear regression of a large number of samples.

Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits

Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.

MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits

Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache leakage. In addition, as technology migrates to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, indicating that leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to reduce leakage in SRAM peripherals by putting them into low-leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an integrated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide leakage control mechanism and switch peripheral circuit's power mode. The results show leakage reduction by up to 40× in deeply pipelined SRAM peripheral circuits, with small area overhead and small additional delay. This noticeable leakage reduction translates to up to 85% overall leakage reduction in on-chip memories.

Efficient Fuzzy C-Means Architecture for Image Segmentation

This paper presents a novel VLSI architecture for image segmentation. The architecture is based on the fuzzy c-means algorithm with spatial constraint for reducing the misclassification rate. In the architecture, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. In addition, an efficient pipelined circuit is used for the updating process for accelerating the computational speed. Experimental results show that the the proposed circuit is an effective alternative for real-time image segmentation with low area cost and low misclassification rate.

Modelling and analysis of pipelined circuit switching in interconnection networks with bursty traffic and hot-spot destinations

Pipelined circuit switching (PCS) that combines the advantages of both circuit switching and wormhole switching is an efficient method for passing messages in interconnection networks. Analytical modelling is a cost-effective tool and plays an important role in achieving a clear understanding of the network performance. However, most of the existing models for PCS are unable to capture the realistic nature of message behaviours generated by real-world applications, which have a significant impact on the design and performance of communication networks. This paper presents a new analytical model for PCS in interconnection networks in the presence of bursty and correlated message arrivals coupled with hot-spot destinations, which can capture the bursty message arrival process and non-uniform distribution of message destinations. Such a traffic pattern has been found in many practical communication environments. The accuracy of the proposed analytical model is validated through extensive simulation experiments. The model is then applied to investigate the effects of the bursty message arrivals and hot-spot destinations on the performance of interconnection networks with PCS.

An Approach for Solving Large SAT Problems on FPGA

WSAT and its variants are one of the best performing stochastic local search algorithms for the satisfiability (SAT) problem. In this article, we propose an approach for solving large 3-SAT problems on FPGA using a WSAT algorithm. In hardware solvers, it is important to solve large problems efficiently. In WSAT algorithms, an assignment of binary values to the variables that satisfy all clauses is searched by repeatedly choosing a variable in an unsatisfied clause using a heuristic, and flipping its value. In our solver, (1) only the clauses that may be unsatisfied by the flipping are evaluated in parallel to minimize the circuit size, and (2) several independent tries are executed at the same time on the pipelined circuit to achieve high performance. Our FPGA solver can solve larger problems than previous works with less hardware resources, and shows higher performance.

SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation

Aggressive technology scaling down and low-power design techniques lead to uneven distributed power density, which translates into heat flow in the chips, causing significant temperature variations in both spatial and temporal terms. In order to mitigate the negative impacts of temperature variations on circuit timing, we propose SACTA, a self-adjusting clock tree architecture, which performs temperature-dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. The dynamic and adaptive features of SACTA are enabled by our proposed automatic temperature-adjustable skew buffers and temperature-insensitive skew buffers. These special delay elements are carefully tuned to ensure resilience of the entire circuit against temperature variation. To determine their configurations, we proposed an efficient and general clock tree design and optimization framework. Furthermore, we show that SACTA is applicable across a wide spectrum of circuits, including multi- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${V}_{\rm dd}/{V}_{\rm th}$</tex></formula> designs. Experimental results show that a pipeline supported by SACTA is able to prevent thermal-induced timing violations within a significantly larger range of operating temperatures (on average, the violation-free range can be enhanced by over 15 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}\hbox {C}$</tex></formula> ).