Pinned Photodiode Research Articles

The Effect of Pixel Design and Operation Conditions on Linear Output Range of 4T CMOS Image Sensors.

We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 μm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 μm pixels and channels B3-B6 are 20 μm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels.

Global shutter CMOS vision sensors and event cameras for on‐chip dynamic information

AbstractThe on‐chip extraction of dynamic information from a scene can be addressed with either frame‐based CMOS vision, also called smart image sensors, or dynamic vision sensors, also known as event cameras. When implemented with a pinned photodiode (PPD) as a 4‐transistor active pixel sensor (4T‐APS), the former brings about the benefits of low temporal noise and dark current but without high dynamic range (HDR). The latter comes with the benefits of HDR and a fast event detection rate with low power consumption. The drawback is the background activity noise, which leads to additional hardware or algorithms to keep it low. This paperanalyses the mismatch and noise of a global shutter 4T‐APS implementation with local HDR through an overflow capacitor and correlated double sampling (CDS) to provide low noise events through frame differencing. The aim is to narrow the gap with dynamic vision sensors in terms of event rate and dynamic range. We show that our solution would be competitive with event cameras in scenarios with slow moving objects and a relatively wide dynamic range (85 dB).

Degradation analysis of the pinned photodiode CMOS image sensors induced by energetic proton radiation

The experiments of the 0.18-μm pinned photodiode (PPD) CMOS image sensors (CISs) irradiated by energetic proton radiation with energies of 20, 40, 60, and 100 MeV are presented. The degradations of the mean dark signal, dark signal non-uniformity (DSNU), and fixed pattern noise (FPN) induced by protons are presented. The experimental results show that the mean dark signal degradations of the CISs decrease with increasing proton energy at the same fluence. The degradations induced by proton radiation at different fluence are also presented. The mean dark signals increase with increasing integration time at the same proton fluence. The degradation mechanisms of the CISs induced by energetic protons are analyzed.

Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity.

In this paper, the light intensity and charge holding time dependence of pinned photodiode (PD) full well capacity (FWC) are studied for our pixel structure with a buried overflow path under the transfer gate. The formulae for PDFWC derived from a simple analytical model show that the relation between light intensity and PDFWC is logarithmic because PDFWC is determined by the balance between the photo-generated current and overflow current under the bright condition. Furthermore, with using pulsed light before a charge holding operation in PD, the accumulated charges in PD decrease with the holding time due to the overflow current, and finally, it reaches equilibrium PDFWC. The analytical model has been successfully validated by the technology computer-aided design (TCAD) device simulation and actual device measurement.

Mathematical model of potential distribution in a pinned photodiode of an indirect time offlightCMOS image sensor.

This paper focuses on the rapid charge transfer of lock-in pixels in time of flight 3D image sensors. Through the principal analysis, a mathematical model of potential distribution in a pinned photodiode (PPD) in different comb shapes is established. Based on this model, the influence of different comb shapes on the accelerating electric field in PPD is analyzed. The semiconductor device simulation tool SPECTRA is applied to verify the effectiveness of the model, and the simulation results are analyzed and discussed. When the width of comb tooth is in narrow and medium range, the potential changes more obviously with the increase of comb tooth angle α, whereas the potential becomes stable even if the comb tooth angle α increases sharply with the wide comb tooth width. The proposed mathematical model contributes to instructing the design of pixel transferring electrons rapidly and resolving image lag.

A simulation result of trapped charge in PPD CIS induced by total ionizing dose effect

This paper describes a method for simulating the total ionizing dose (TID) radiation effect of a PPD CMOS image sensor (CIS) using TCAD. This paper takes the CIS pixel unit as the research object, modeling the device structure and combining it with a gamma radiation model to simulate the distribution of radiation-induced charge generation rate, electron concentration, and potential at each interface in the entire region before and after irradiation with TID equal to 5, 20, 50, 80, 100, 200, and 300 krad(Si). At the same time, the curves of the above parameters changed with the increase of TID radiation have been simulated. Furthermore, the influence of different TIDs on the parameters mentioned above at each interface has been investigated based on the two main damage mechanisms of the TID radiation effect: radiation-induced oxide trapped charge and radiation-induced interface trapped charge. It was also discovered that as the TID increases, the depletion region of the pinned photodiode (PPD) becomes broader, causing the dark current to increase.

Influence of Pixel Design on Charge Transfer in Pinned Photodiode CMOS Image Sensors

The influence of pixel design on charge transfer, mainly on potential barrier and potential pocket, is investigated in this paper. By simplifying the interface region between the pinned photodiode (PPD) and the transfer gate (TG), an intuitive and simple method for analyzing the potential barrier and pocket is presented. Through TCAD simulations, the validity of the analysis method is verified, and the influence of some key dimension and process parameters in PPD pixel design on the potential barrier and pocket is clarified. The whole study help improve the understanding of the charge transfer limitation mechanism, and can achieve high charge transfer efficiency and low image lag noise in the PPD pixel design of CMOS image sensors (CISs).

The effect of photodiode shape on pinning potential for charge transfer in CMOS image sensors

The effect of the pinned photodiode (PPD) shape on charge transfer has been investigated in this paper. By equating the change in pinning potential distribution due to PPD shape to the decrease in depth of the depletion region in the vertical direction, an analytical model of the PPD shape effect on the pinning potential is proposed. The model for a triangular-like PPD is validated by TCAD simulations and is in very good agreement with the simulation results. Based on the model results, a tower-shaped PPD shape that can obtain constant lateral electric field is given. Simulation results show that the tower-shaped PPD have good pinning potential variation linearity and much better charge transfer performance than rectangular and triangular PPDs. The model and analysis results in this paper provide theoretical support and design ideas for the shape design and optimization of PPD-based pixels to improve the charge transfer speed and reduce the image lag.

TCAD Calibration at Cryogenic Temperatures for CMOS Image Sensor Simulations

A simple calibration method is presented for the technology computer-aided design (TCAD) simulation at cryogenic temperature, with a special focus on image sensor application. Based on the principle that TCAD tools are not completely mature for cryogenic environment, a calibration is needed to perform reliable simulations. In this work, measurements and simulations of sheet resistances are used for the TCAD calibration, and an experimental verification is performed by means of the extraction of pinning voltages on JFETs and on a pixel including a pinned photodiode (PPD).

Analytical Modeling of Potential Barrier for Charge Transfer in Pinned Photodiode CMOS Image Sensors

A potential barrier is one of the most common lag sources for charge transfer in pinned photodiode (PPD) CMOS image sensors (CISs). In this article, an analytical model of the potential barrier is proposed for the PPD combined with the transfer gate (TG). Through detailed electrostatic analysis of the PPD and TG, the potential barrier is analytically expressed as a function of the doping concentrations, TG voltage, spatial dimensions, and other physical parameters. The proposed model is validated by technology computer-aided design (TCAD) simulations, and the results show that the model data are in good agreement with the TCAD simulations in terms of the magnitude and location of the potential barrier. The model can be used for the design, simulation, and optimization of PPD-based pixels in CISs to improve the charge transfer efficiency (CTE) and reduce the image lag noise.

Analytical Model of the Vertical Pinned Photodiode

This article presents a simple analytical model of the vertical pinned photodiode (PPD). In the existing pixels with relatively large sizes, the photodiode is formed byp+-n-p doping in a planar manner, and thus the vertical electric field determines the potential of the photodiode. However, as the pixel size becomes smaller, the size of the photodiode also decreases. Accordingly, the influence of the doping concentration in the periphery becomes larger and the pinning voltage is eventually predominantly determined by the horizontal electric field in the submicrometer region. In this case, the analytical model describing the conventional photodiode structure is no longer applicable. Therefore, in this article, a simple analytical model applicable to a small pixel size is provided and verified through TCAD simulation. It is thought that the proposed simple model helps understand the potential of small pixel size and provides a major starting point for design.

BJT induced dark current in CMOS image sensors

This paper demonstrates that cut-off pnp Bipolar Junction Transistors (BJTs) can induce visible dark current to their nearby CMOS (Complementary Metal Oxide Semiconductor) image sensor pixels, supported with experimental results. Previously, it has been shown that active BJTs and forward-biased PN junctions can incur dark shading to nearby CMOS image sensor pixels through electroluminescence (EL). However, in our experiments, when the BJTs are in their cut-off region, they can induce dark current to nearby image pixels at a similar distance but the dark current level declines much faster. To figure out the causes of dark current induced by the cut-off BJTs, the thermal coefficient of their nearby image pixels has been measured and the current is found to double for every 5 °C temperature rise. This indicates the cut-off BJT induced dark current is mainly due to the diffusion current generated from the silicon neutral regions in the pinned photodiodes (PPDs). This is in contrast to the hot pixels’ dark current incurred by thermal generation, that doubles for every 10 °C increase in temperature, or EL that has a very small thermal coefficient.

Probing Dark Current Random Telegraph Signal in a Small Pitch Vertically Pinned Photodiode CMOS Image Sensor After Proton Irradiation

The dark current degradation and dark current random telegraph signal (DC-RTS) after proton irradiation are studied in new scale silicon microvolumes by using a commercial CMOS image sensor. Results show that previously reported empirical models describing the displacement damage-induced degradations are still valid despite the 10–100 times smaller depletion volume used. In addition, no evidence of significant total ionizing dose effects is observed. Finally, the reduction of the fraction of RTS pixels detected and the fraction of multilevel RTS pixels is directly linked to the reduction in pixel volume.

A simulation study of electric field engineering with multi-level pinned photodiodes for fast and complete charge transfer

In a CMOS image sensor pixel, fast and complete charge transfer from pinned photodiode (PPD) is desired and necessary in some applications. In special cases such as time-of-flight imaging or large pinned photodiodes, the PPD potential well shape greatly affects the charge transfer performance and should be engineered carefully. In the present work, a PPD structure named as multi-level PPD is introduced and examined through simulation study. Moreover, a fast and effective way to analyze the pinning process for a lag-free design is introduced. It is concluded that the proposed PPD achieves fast and complete charge transfer without employing additional lithography masks or process steps. The proposed PPD is compared with a similar conventional rectangular pixel and 31% reduction in the charge transfer time is observed.

MOS-based model of four-transistor CMOS image sensor pixels for photoelectric simulation

By using the MOS-based model established in this paper, the physical process of photoelectron generation, transfer, and storage in the four-transistor active pixel sensor (4T-APS) pixels can be simulated in SPICE environment. The variable capacitance characteristics of double junctions in pinned photodiodes (PPDs) and the threshold voltage difference formed by channel nonuniform doping in transfer gates (TGs) are considered with this model. The charge transfer process of photogenerated electrons from PPDs to the floating diffusion (FD) is analyzed, and the function of nonuniform doping of TGs in suppressing charge injection back to PPDs is represented with the model. The optical and electrical characteristics of all devices in the pixel are effectively combined with the model. Moreover, the charge transfer efficiency and the voltage variation in PPD can be described with the model. Compared with the hybrid simulation in TCAD and the Verilog-A simulation in SPICE, this model has higher simulation efficiency and accuracy, respectively. The effectiveness of the MOS-based model is experimentally verified in a 3 μm test pixel designed in 0.11 μm CIS process.

A General Compact Pinned Photodiode Model Capable of Miniature PPD Modeling

This article presents a simple yet powerful general pinning process model for 3-D pinned photodiodes (PPDs), which can be used to model PPDs with small dimensions (miniature PPDs). For the development of a pinning model, capable of dealing with different PPD shapes and dimensions, the charge population in the space charge region (SCR) is calculated. Moreover, to improve the model’s accuracy, the PPD inner region depletion mechanism is investigated, and the inner SCR width is extracted analytically. The model’s application in analyzing PPDs is verified with six previously published experimental results.

Analysis of Charge Transfer Potential Barrier in Pinned Photodiode of CMOS Image Sensors

The full well capacity (FWC) and the pinned photodiode (PPD) capacitance of four-transistor pixel in a CMOS image sensor are reported to be dependent on the potential barrier offered by transfer gate (TG). The asymmetrical TG channel potential increases the effective potential barrier, thereby increasing the FWC and decreasing the feedforward charges. At the PPD-TG interface, a potential pocket can exist, the influence of which is minimized to lower the image lag. In the presence of a potential pocket, two charge transfer potential barriers (CTPBs) are present in the charge transfer path. The combined effect of the two potential barriers is higher than the single barrier reported in the literature. The CTPB depends on the number of integrated PPD charges and influences the FWC and PPD capacitance. The improved PPD capacitance model matches well with the measurement results when the influence of potential pocket on CTPB is considered.

Dynamic Model of FWC Dependent on the Energy-Level Distribution of Interface-State Traps in Pinned Photodiodes

Full well capacity (FWC) modeling has been widely used to clarify the imaging characteristics of the pinned photodiode (PPD) in complementary metal-oxide-semiconductor (CMOS) image sensors. Until now, FWC modeling has considered only the effects of temperature, doping, and photon dependence on the FWC. However, the influence of the distribution of interface trap-state energy levels on the FWC is ignored. Therefore, this article proposes a dynamic FWC model that depends on the energy-level distribution of interface trap states in a PPD for the first time. By establishing a 2-D function for the reverse saturation current related to the trap-state density and trap energy level, an explicit 2-D expression is derived for the full well potential associated with trap-state density and trap energy level. According to the relationship between the full well potential and FWC, as well as the relationships among the trap-state density, trap energy level, and trap energy-level distribution, a dynamic model of the FWC is deduced that depends on the trap energy-level distribution. The consistency between results of TCAD simulations and our theoretical model shows that the FWC is not a single fixed value but a set of dynamic values that change with the distribution of trap energy levels.

Degradation characteristics of γ-ray and proton irradiated 8T CMOS image sensors

The degradation of a pinned photodiode (PPD) 8T CMOS image sensor (8T-CIS) due to total ionizing dose (TID) and displacement damage dose (DDD) have been investigated with γ-ray and proton irradiation. The dark current and its distributions were studied. We observed a significant increase in the dark current after the proton irradiation than that after the γ-ray irradiation. We observed that the peak values in the Gaussian distribution shift to higher values as a result of TID effects while comparing the dark current distribution results of the γ-ray and proton irradiation. In contrast, the hot pixel tailing increases with the DDD effect. At the same time, the degradation of the light response of the device was investigated by observing the quantum efficiency in the wavelength range of 420–800 nm. A comparison of the results obtained from the γ-ray and proton irradiations showed that the short-wavelength degradation was caused by the TID whereas the DDD caused the degradation in the full spectral range.

Single Event Effects in 0.18 μm Pinned Photodiode CMOS Image Sensors: SEU and SEFI

CMOS Image Sensors (CISs) can easily be susceptible to heavy-ion radiation in space applications. The sensitivity of Single Event Effect (SEE) in CIS is explored by heavy ion broad beam experiments and laser experiments. Pinned Photodiode (PPD) CMOS Image Sensors were exposed to heavy ions with Linear Energy Transfer (LET) (8.62–81.35 MeV cm2 mg−1). The digital peripheral circuits of CIS studied were found sensitive to heavy-ion-induced Single Event Upset (SEU) and Single Event Function Interrupt (SEFI). The vulnerable elements of digital peripheral circuits are identified by the analysis of the corrupted images under heavy ion beam and positioning function of laser experiment. Some SEE-induced corruption images that were not reported before are presented in this paper. Results showed that row decoder, digital control signals and Serial Peripheral Interface (SPI) registers in CIS studied are sensitive to SEU and SEFI.