Analysis of Charge Transfer Potential Barrier in Pinned Photodiode of CMOS Image Sensors

Abstract

The full well capacity (FWC) and the pinned photodiode (PPD) capacitance of four-transistor pixel in a CMOS image sensor are reported to be dependent on the potential barrier offered by transfer gate (TG). The asymmetrical TG channel potential increases the effective potential barrier, thereby increasing the FWC and decreasing the feedforward charges. At the PPD-TG interface, a potential pocket can exist, the influence of which is minimized to lower the image lag. In the presence of a potential pocket, two charge transfer potential barriers (CTPBs) are present in the charge transfer path. The combined effect of the two potential barriers is higher than the single barrier reported in the literature. The CTPB depends on the number of integrated PPD charges and influences the FWC and PPD capacitance. The improved PPD capacitance model matches well with the measurement results when the influence of potential pocket on CTPB is considered.