Model Of Phase-locked Loop Research Articles

UNIVERSAL PROGRAMMABLE CHAOS GENERATOR: DESIGN AND IMPLEMENTATION ISSUES

Chaos generators are generally designed and implemented by using analog circuit design techniques. Analog implementations require a variety of circuitry that comprises different passive and active electronic components like individual op-amps, comparators, analog multipliers, trigonometric function generators. Anyone who wants to experimentally investigate different structurally chaotic systems has to provide a significant amount of circuit hardware. This process may be hard and time consuming. At this stage, the question to be asked: Is there a unique analog component for implementing a universal analog chaos generator which is capable of generating the chaotic signals of nearly all analog-based chaotic systems. Fortunately, we can now answer this question positively. This analog device is FPAA (Field-Programmable Analog Array). FPAA is the analog equivalent of the FPGA (Field-Programmable Gate Array) used as programmable device in digital signal processing. FPAA is a programmable device for implementing a rich variety of systems including analog functions via dynamic reconfiguration. FPAA can be configured in real time which allows the designers to modify the design or make completely new design in real time. In this paper, we aim to show how FPAA device can be used as universal device for design and implementation of programmable analog chaos generators. For this purpose, we will introduce three FPAA-based design examples: autonomous Chua's circuit, nonautonomous MLC (Murali–Lakshmanan–Chua) circuit and a chaotic system based on a PLL (Phase Locked Loop) model.

A low-noise PLL design achieved by optimizing the loop bandwidth

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

Modeling and analysis of single-event transients in charge pumps

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phase-locked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.

52 Gb/s 16:1 transmitter in 0.13 µm SiGe BiCMOS technology

A52-Gb/s 16:1 quarter-rate clocking transmitter for high-speed serial data transmission is designed to utilise 0.13-mum SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The quarter-rate transmitter consists of a 16:1 multiplexer (MUX), a voltage-controlled ring oscillator, a phase-locked loop (PLL), a pseudorandom data generator and an output amplifier. The voltage-controlled ring oscillator has a wide tuning range from 11 to 22 GHz with feedforward loop and delay interpolation. A continuous model of a third-order PLL is developed and used to optimise loop filter parameters and to estimate the PLL performance in a simulation. The PLL achieves a low phase noise of -124.6 dBc/Hz at 1 MHz offset. The 16:1 MUX features quarter-rate clock multiplexing with multi-phase voltage-controlled oscillator clocks. In the design of a 16:1 MUX, an edge-channelling 4:1 MUX is used to alleviate a duty cycle and a jitter problem.

Spectral properties of phase-locked flux flow oscillator

In the present paper, the results of theoretical modeling of flux flow oscillator (FFO) included into phase-locked loop (PLL) system and its comparison with experiment are outlined. To describe theoretically the dynamics of phase-locked FFO, we have considered two models: first order PLL system and the PLL system with integral-proportional filter. While the first order PLL system may be treated analytically even in the frame of nonlinear PLL model and gives satisfactory agreement with experimental results, it does not describe all peculiarities of spectral density, which may be described well by a more sophisticated model with the integral-proportional filter. The quantitative prediction of spectral ratio improvement due to increase of PLL regulation bandwidth is given.

Study on chaos control of second-order non-autonomous phase-locked loop based on state observer

With system parameters falling into a certain area, the second-order non-autonomous phase locked loop (PLL) is experiencing chaotic behavior which is undesirable in system, where it is necessary to estimate the phase of a received signal. In order to control chaos in PLL and drive it to the locked state, dynamical equation for phase error model of PLL is firstly derived. Then, the state values of phase and transient frequency errors were estimated by a state observer. Moreover, by exploiting these state estimations, a non-linear feedback controller is designed. Since the presented controller does not need to change the controlled system structure and not to use any information of system except the system state variables, the designed controller is simple and desirable. Simulation results show that the presented control law is very effective.

Speeding up an integer-N PLL by controlling the loop filter charge

This paper studies a group of methods designed to speed-up the frequency step response of integer-N phase-locked loops (PLLs). The methods are based on current signals connected to the loop filter. Optimal speed-up waveforms are found mathematically using a linear PLL model. The paper also discusses problems associated with this theoretical waveform and introduces a considerably simpler waveform based on the use of two current pulses. This method uses excess output frequency to quickly cancel the accumulated phase error. In order to accelerate the decay of the phase error, the PLL is first overdriven at the beginning of the frequency transition with an external charge pulse to the loop filter. As the phase error goes rapidly to zero, the frequency error is also reduced to zero by another charge pulse. The theory presented here is verified by measurements using a practical RF synthesizer.

A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis

A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.

Performance of Coherent Optical PSK Systems with Costas Loop in Receiver for Nonlinear Second-Order PLL Model

Using the nonlinear second-order PLL (phase-locked loop) model, the authors consider the performance of the coherent optical PSK (phase-shift keying) systems with Costas loop in receiver, for the first time. The shot noise of the corresponding PIN photodiodes is described through the signal-to-noise ratio in the loop bandwidth, and the laser phase noise is described through the normalized frequency fluctuations instead of the phase ones. The analysis is carried out for both homodyne and heterodyne types of receivers. The theory and results presented in this article can be applied to the analysis and optimization of performance in regions where the linear PLL model is not sufficient.

A low-noise phase-locked loop design by loop bandwidth optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

Performance Optimization and Laser Linewidth Requirement Evaluation for a Coherent Optical Psk System With DDL

This paper presents the exact requirement laser linewidth evaluation for both heterodyne and homodyne receivers with a Decision-Driven Loop (DDL). Taking the laser phase noise and photodetector shot noise into account, the Probability Density Function (p.d.f.) of the phase error is determined. The optimal normalized loop bandwidth is determined by minimizing the Bit-Error Rate (BER). The power penalty dependence on laser linewidth is also determined. All calculations are based on the nonlinear Phase-Locked Loop (PLL) model. The laser phase noise and photodiode shot noise are described through loop parameter variations. The laser phase noise is presented specifically through frequency variations of both the transmitter laser and the local laser instead of phase fluctuations. Finally, the comparison between nonlinear phase loop model results determined here and linear phase loop model results obtained in [1, 2] is presented.

Phase-locked operation of RSFQ ring oscillators

Ring oscillators are the traditional on-chip clock source for RSFQ mixed-signal and digital circuits. Their long-term frequency stability is essential for certain signal processing applications such as the sampling clock for an A/D converter or the output clock of a D/A converter. However conventional bias schemes lead to excessive drift in the frequency. Embedding the ring oscillator in a phase-locked loop (PLL) circuit allows it to inherit the frequency stability of an external reference source. An RSFQ circuit comprised of a ring oscillator, a divide-by-220 prescaler and a resynchronizer D flip-flop was fabricated using the standard 1 kA cm-2 niobium foundry service from Hypres. The circuit was stabilized using a low-frequency PLL with a bandwidth of 6 Hz. The output of the phase detector in the PLL was used to produce a feedback current that stabilized the frequency of the ring oscillator at around 8 GHz. The frequency spectrum of the RSFQ scaled oscillator output was measured in open- and closed-loop configurations. Compared to the open-loop phase noise spectrum the closed-loop spectrum showed a decrease of 30 dB of the oscillator phase noise at an offset of 1 Hz from the divided-down carrier frequency of 4.1 kHz. This agreed with the classical phase-locked loop model for the system. The long-term frequency drift of the RSFQ clock was determined by the stability of the oven-controlled quartz oscillator used as the reference in the PLL.

Performance of optical heterodyne PSK systems with Costas loop in multichannel environment for nonlinear second-order PLL model

Using the nonlinear second-order phase-locked loop (PLL) model the performance of the heterodyne coherent optical phase shift keying (PSK) systems with Costas loop in multichannel environment is considered in this paper for the first time. The shot noise of the corresponding photodiodes and adjacent channel interferences are described through the signal-to-noise ratio (SNR) in the loop bandwidth, while the laser phase noise is described through the normalized frequency fluctuations instead of the phase ones. The theory and results presented in this paper can be applied when analyzing and optimizing the performance in the region where the linear PLL model is not enough good.

Influence of imperfect carrier recovery on satellite QPSK communication system performance

The purpose of this paper is to provide the theoretical approach for determining the bit error probability in detecting a coherent quaternary phase-shift-keyed signal transmitted over a soft-limited channel in the presence of the uplink and downlink noise, as well as the noisy carrier reference signal. The uplink noise is considered in the specific way through the envelope variations and the frequency offset of the signal remitted by the satellite station having influence on the variations of the phase-locked loop parameters in the receiving ground station, consequently on the probability density function of the phase error, i.e. the average bit error probability. The downlink noise is also taken into consideration. The determined results are based on the non-linear phase-locked loop model with primary emphasis on the degradations in the system performance produced by the imperfect carrier signal extraction. Copyright © 1999 John Wiley & Sons, Ltd.

Temporal-code to rate-code conversion by neuronal phase-locked loops.

Peripheral sensory activity follows the temporal structure of input signals. Central sensory processing uses also rate coding, and motor outputs appear to be primarily encoded by rate. I propose here a simple, efficient structure, converting temporal coding to rate coding by neuronal phase-locked loops (PLL). The simplest form of a PLL includes a phase detector (that is, a neuronal-plausible version of an ideal coincidence detector) and a controllable local oscillator that are connected in a negative feedback loop. The phase detector compares the firing times of the local oscillator and the input and provides an output whose firing rate is monotonically related to the time difference. The output rate is fed back to the local oscillator and forces it to phase-lock to the input. Every temporal interval at the input is associated with a specific pair of output rate and time difference values; the higher the output rate, the further the local oscillator is driven from its intrinsic frequency. Sequences of input intervals, which by definition encode input information, are thus represented by sequences of firing rates at the PLL's output. The most plausible implementation of PLL circuits is by thalamocortical loops in which populations of thalamic "relay" neurons function as phase detectors that compare the timings of cortical oscillators and sensory signals. The output in this case is encoded by the thalamic population rate. This article presents and analyzes the algorithmic and the implementation levels of the proposed PLL model and describes the implementation of the PLL model to the primate tactile system.

Z-domain model for discrete-time PLL's

The well-known s-domain model for continuous-time phase-locked loops (PLLs) is a fundamental tool for the linearized analysis of these systems. For PLLs with digital inputs and outputs, however, a discrete-time z-domain model more accurately describes loop behavior. In this study, a methodology is described for obtaining an accurate z-domain description of a discrete-time PLL. The modeling technique transforms portions of the s-domain PLL model directly into the z-domain, requiring only straightforward algebraic manipulations even for complex loop filters. This methodology is demonstrated for a simple loop filter, and measurements from the digital signaling interface integrated circuit are used to compare s-domain, z-domain, and time-step analysis results for a more complicated loop filter. The z-domain model, although only incrementally more complicated than the s-domain model, is shown to be more accurate, especially at higher jitter frequencies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digital Phase-Locked Loop Behavior with Clock and Sampler Quantization

This paper deals with the analysis of digital phase-locked loop (DPLL) models that take into account the discrete nature of the analog-to-digital converter (ADC) and the numerical controlled oscillator (NCO). The models are general enough to allow for different kinds of noise distributions and nonuniform qnantization. Weak assumptions on the nature of the loop parameters reduce the models to finite Markov chain problems. It is shown that the resulting probability transition matrices are lumpable, which translates into convenient Computational savings. In this manner, an exact statistical analysis is possible not only for first-order but also for second-order loops. Numerical results give evidence that for appropriate ADC and NCO characteristics, few quantization levels are needed to match the performance of models that ignore qnantization. However, when the values of these characteristics are not proper, a substantial change in performance can occur. This change in the loop behavior cannot be analyzed or predicted by those models that neglect the quantization effects. It is also found that the use of a nonlinear ADC improves the loop behavior when the noise density distribution is heavy-tailed, e.g., atmospheric noise.

Phase-Locked Loops with Limiter Phase Detectors in the Presence of Noise

A nonlinear mathematical model of phase-locked loops with limiter phase detectors in the presence of noise is presented. The model, which is an extension of the well-known baseband model of loops with sinusoidal phase detectors without limiters, incorporates a modified nonlinear phase detector characteristic, the form of which is changed if the input carrier-to-noise ratio alters, as well as a modified phase noise as an input to the model. Both the modified phase detector characteristic and the spectral density of the modified noise term are calculated specifically for sinusoidal, triangular, and sawtooth types of limiter phase detectors, allowing the application of various methods to determine the loop noise performance. As an example, the phase error variance of a first-order phase-locked loop is calculated, thereby showing a strong dependence on the specific phase detector realization.

Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise

Digital phase-locked loops of the type employing discrete phase adjustments form an interesting class for which both steady-state and transient performance may be determined in the presence of additive white Gaussian noise. A general technique for obtaining this analysis is presented. A class of sequential filters is described that appears to be well suited to this type of loop. Their performance is characterized by a variable number of inputs per output (depending upon the input sequence) and the use of coarse quantization. Two specific examples are discussed. The closed-loop transient analysis shows these loops to have effectively a slew-rate limited phase adjustment, indicating that they are decidedly nonlinear. A digital loop quasi-bandwidth measure is defined in terms of this transient response. This definition allows the comparison of digital loops on a basis of equal signal-to-noise ratios within the loop bandwidth and, to a limited extent, makes possible a similar comparison of the digital loops with linear loops. Performance of the digital loops is found to be similar to that of the first-order linear phase-locked loop model for low loop bandwidth signal-to-noise ratio but reaches a limiting minimum phase error due to quantization of the phase adjustments for high signal-to-noise ratio. This limit, however, can be set as low as desired by choosing a small enough phase-correction quantum. The digitalloop bandwidth is found to vary with the signal energy per noise spectral density ratio rather than with the signal amplitude as in the case of the linear analog model.

Achievement of rate-distortion bound over additive white noise channel utilizing a noiseless feedback channel

A linear system utilizing a noiseless feedback channel is shown to achieve the rate-distortion bound on performance. The result follows from the previous study of linearized phase-locked loop models.