Model Of Phase-locked Loop Research Articles

Compact Modeling of Phase-Locked Loop Frequency Synthesizer for Transient Phase Noise and Jitter Simulation

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process.

Impedance-Based Analysis of Grid-Synchronization Stability for Three-Phase Paralleled Converters

Grid synchronization stability issues and subsynchronous oscillations between synchronous generators exist in electrical power systems. Three-phase voltage-source converters (VSCs) are being installed more and more in the grid to improve efficiency or to utilize renewable energy sources. The same stability issues between VSCs are also reported and analyzed using a small-signal model of phase-locked loops (PLLs). This paper proposes a different impedance-based analysis method. The proposed method shows that synchronization instability in a VSC system is due to the negative incremental resistance behavior of grid-tied inverters' impedance when they are modeled in the d-q frame. System can be stabilized simply by changing the inverter's PLL design. Experimental results verify the analysis and the proposed method.

Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA

提出了一种新型的全数字锁相环，其采用自采样比例积分控制，使得锁相输出无静差，输出抖动小，并能根据数字鉴相器输入信号间相位误差的大小，调节数字环路滤波器的计数模数，在保证锁相环稳定性的同时，提高了锁相环锁定速度。本文基于该全数字锁相环各模块工作特性的分析，建立了全数字锁相环的数学模型，利用所得到的锁相环系统传递函数进行了性能参数分析，并给出了锁相环参数设计指导原则。论文最后通过实验测试验证了理论参数分析的正确性。 This paper proposed a novel all-digital phase-locked loop (ADPLL). By using the self-sampling PI control method, it can obtain a phase-locked output signal without steady-state error and with less jitter. The designed ADPLL is able to adjust the mode number of the digital loop filter according to the phase error between the two input signals of the digital phase detector. In this way, the ADPLL can optimize the lock-in speed when the system stability is also guaranteed. The paper establishes the mathematical model of the ADPLL based on the analysis of the operating characteristic of each module. Using the obtained system transfer function, the paper analyzes the performance parameters of the ADPLL, and provides the guiding principle of the parameters design. The validity of theoretical analysis is verified by experimental test in the final of this paper.

Modeling and verifying the impact of time delay on INS-aided GNSS PLLs

The timing error between global navigation satellite system (GNSS) and inertial navigation system (INS) processes limits the integration performance in GNSS/INS integrated systems. In a deeply coupled system, this timing error affects not only the integrated navigation solution, but also the GNSS signal tracking. We propose a time-domain model of INS-aided second-order phase-locked loops (PLLs) in consideration of the INS aiding delay, and analyze the effect of INS aiding delay on the tracking errors in details. In addition, an integrated hardware deeply coupled system platform was developed to verify the impact of time delay on INS-aided PLLs. Simulation and field vehicles testing results demonstrate that the tracking error of the INS-aided PLL caused by aiding delay increases with the lengthening of the delay time, the compression of the bandwidth, and the increase in the acceleration. Testing results verify the proposed model.

Supply-Noise Interactions Among Submodules Inside a Charge-Pump PLL

Behavioral models are necessary to shorten the design turn-around time of phase-locked loops (PLLs). For general cases in a system-on-chip, the PLL can resist the supply noise from other modules by a low-dropout regulator. Therefore, interactions among the supply ports of PLL submodules play a much more important part in the overall noise performance. In this brief, we propose a time-domain charge-pump PLL model including supply-noise interactions inside PLL. Described by Verilog-A, the behavioral results are compared with the simulated results of transistor circuits. It can be seen that the proposed model has reduced the simulation time to about 1.7% when compared with transistor-level simulating by SpectreRF. Under a nonideal power grid, our model can improve the jitter simulation accuracy when compared with the conventional model, e.g., simulated jitter error is lowered by 52.6% under a power grid with 8- $\Omega $ power-line segment and 1-pF decoupling capacitance.

Analysis of Phase-Locked Loop Low-Frequency Stability in Three-Phase Grid-Connected Power Converters Considering Impedance Interactions

Synchronous reference frame (SRF) phase-locked loop (PLL) is a critical component for the control and grid synchronization of three-phase grid-connected power converters. The PLL behaviors, especially its low-frequency dynamics, influenced by different grid and load impedances as well as operation mode have not been investigated yet, which may not be captured by conventional linear PLL models. In this paper, we propose a state-feedback quasi-static SRF-PLL model, which can identify and quantify the inherent frequency self-synchronization mechanism in the converter control system. This self-synchronization effect is essentially due to the converter interactions with grid impedance and power flow directions. The low-frequency nonlinear behaviors of the PLL under different grid impedance conditions are then analyzed, which forms the framework of evaluating the impacts of the large penetration level of distributed generation units, weak grid, microgrid, and large reactive power consumption in terms of the frequency stability of PLL. Specifically, the PLL behavior of the converter system under islanded condition is investigated to explain the PLL instability issues and the related islanding-detection methods in early publications and industry reports.

Mathematical model of the phase-locked loop with a current detector

The mathematical model of the pulses phase-locked loop (PLL) with a frequency-phase detector and a current pump, which is represented as a set of difference and transcendental equations and relies on the dynamics of the given deterministic system (in the general case, an arbitrary-order loop filter) described by an automation with a finite number of components and combined differential equations, is examined. An algorithm describing the operation of the in-lock indicator of the given PLL is proposed. The particular cases of the first- and second-order loop filters are discussed. PLL simulation is performed under transient conditions.

Design and Implementation of Pll Frequency Synthesizer using PE3336 IC for IRS Applications

The design and experimental verification of a low phase noise phase locked loop (PLL) frequency synthesizer using Peregrine’s PE83336 IC is presented. This PLL is used as frequency synthesizer which generates stable and low phase noise signal for space applications. A stable reference frequency of 22.8MHz is provided to the PLL through a temperature compensated crystal oscillator (TCXO). Experimental results of the PLL frequency synthesizer shows the excellent performance achieved at Xband. The PLL model implemented with frequency resolution of 5.8MHz, and phase noise better than 81dBc/Hz @ 1 kHz offset at X-band. The complete model is fabricated on RT-duroid 6010 substrate.

Nonlinear analysis of classical phase-locked loops in signal's phase space

Discovery of undesirable hidden oscillations, which cannot be found by the standard simulation, in phase-locked loop (PLL) showed the importance of consideration of nonlinear models and development of rigorous analytical methods for their analysis. In this paper for various signal waveforms, analytical computation of multiplier/mixer phase-detector characteristics is demonstrated, and nonlinear dynamical model of classical analog PLL is derived. Approaches to the rigorous nonlinear analysis of classical analog PLL are discussed.

Formal verification of phase-locked loops using reachability analysis and continuization

We present a scalable and formal technique to verify locking time and stability for charge-pump phase-locked loops (PLLs). In contrast to the traditional simulation approach that only validates the PLL at a given operation condition, our proposed technique formally verified the PLL at all possible operation conditions. The dynamics of the PLL is described by a hybrid automaton, which incorporates the differential equations of the analog circuit elements as well as the switching logic of the digital circuit elements. Existing methods for computing reachable sets for hybrid automata cannot be used to verify the PLL model due to the large number of cycles required for locking. We develop a new method for computing effective overapproximations of the sets of states reached on each cycle by using uncertain parameters in a discrete-time model to represent the range of possible switching times, a technique we call continuization . Using this new method for reachability analysis, it is possible to verify locking specifications for a charge-pump PLL design for all possible initial states and parameter values in time comparable to the time required for a few simulation runs of the same behavioral model.

Nonlinear analysis of phase-locked loop with squarer

The phase-locked loop with squarer is a classical phase-locked loop (PLL) based carrier recovery circuit. Simulation of the loop is nontrivial task, because of high-frequency properties of considered signals. Simulation in space of signals’ phases allows one to overcome these difficulties, but it is required to compute phase detector characteristic. In this paper for various waveforms of high-frequency signals new classes of phase detector characteristics are computed for the first time. The problems of rigorous mathematical analysis of the control signal of voltage-controlled oscillator are discussed. Nonlinear model of PLL with squarer is constructed.

Analytical Method for Computation of Phase-Detector Characteristic

Discovery of undesirable hidden oscillations, which cannot be found by simulation, in models of phase-locked loop (PLL) showed the importance of development and application of analytical methods for the analysis of such models. Approaches to a rigorous nonlinear analysis of analog PLL with multiplier phase detector (classical PLL) and linear filter are discussed. An effective analytical method for computation of multiplier/mixer phase-detector characteristics is proposed. For various waveforms of high-frequency signals, new classes of phase-detector characteristics are obtained, and dynamical model of PLL is constructed.

A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS

Abstract The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

An LMI-Based Method for Reference Spur Reduction in Charge-Pump Phase-Locked Loops Containing Loop Delay

This paper presents a loop-filter design method for third-order charge-pump phase-locked loops containing the loop delay. This method is derived from a z-domain phase-locked loop model. For a given loop bandwidth, we employ ripple swing control and adjust the filter pole to improve the spur performance. Another dynamic specification, the jitter peaking, is formulated as a H ∞ performance. The loop-filter design is transformed into an H ∞ optimization problem with the ripple swing constraint, which is solved using convex programming skills (linear matrix inequality, LMI). Compared to the conventional method, the method proposed in this study offers greater spur reduction without altering the loop bandwidth.

Nonlinear behavioural model of charge pump PLLs

SUMMARY Despite the nonlinear nature of even the simplest versions of phase locked loops (PLLs), linear models are still used during the first phases of the design of modern PLLs. Even though the linear model may represent a crude approach, its use is justified by the fact that accurate numerical simulations often require a too large amount of CPU time, being PLLs by construction stiff circuits, characterised by very different time scales. This aspect has triggered the need for compact models that allow fast and accurate numerical simulations. The scientific literature numbers several models that have been developed with different approaches and tailored to different simulation environments. In this context, we propose a nonlinear model of a type-II PLL, which (1) considers both the switching behaviour of the phase/frequency detector and charge pump and the complex dynamics (including the presence of amplitude and phase noise) of the voltage controlled oscillator, (2) is compact and can be easily implemented in modern mixed analog/digital simulators as a behavioural block, and (3) allows the simulation of spurs owing to the nonlinearities of both the charge pump and the fractional frequency divider. Copyright © 2012 John Wiley & Sons, Ltd.

Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The Peripheral Component Interconnect Express (PCIe) protocol handles all communcation between the central processing unit (CPU) and hardware devices. PCIe buses require efficient clock data recovery circuits (CDR) to recover clock signals embedded in data during transmission. This paper describes the theoretical modeling and simulation of a phase-locked loop (PLL) used in a CDR circuit. A simple PLL architecture for a 5 GHz CDR circuit is proposed and elaborated in this work. Simulations were carried out using a Hardware Description Language, Verilog-AMS. The effect of jitter on the proposed design is also simulated and evaluated in this work. It was found that the proposed design is robust against both input and VCO jitter.ABSTRAK: Sistem komunikasi dan komputer moden memerlukan pemindahan data yang cekap (Gbps), dan bandwidth yang besar. Pengecilan agresif menggunakan teknik sistem digital bersepadu membenarkan bas dan litar pengawal komunikasi disatukan dengan mikroprocessor dalam cip yang sama. Protokol persisian komponen sambung tara ekspres (PCIe) mengendalikan semua komunikasi antara unit pemprosesan pusat (CPU) dan peranti perkakasan. Bas PCIe memerlukan litar jam pemulihan data (CDR) yang cekap untuk mendapatkan kembali isyarat jam yang tertanam dalam data semasa transmisi. Karya ini menerangkan teori pemodelan dan simulasi gelung fasa terkunci (PLL) untuk CDR. Rekabentuk 5 GHz PLL yang mudah telah dicadangkan dalm kertas kerja ini. Simulasi telah dijalankan menggunakan perisian verilog-AMS. Simulasi mengunnakan kesan ketar dalam reka bentuk yang dicadangkan telah dinilai. Reka bentuk yang dicadangkan terbukti teguh mengatasi ganguan ketar di input dan VCO.KEY WORDS: phase-locked loop (PLL); jitter; phase detector; low-pass filter; voltage-controlled oscillator

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.

A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters

Type-II charge-pump (CP) phase-locked loop (PLLs) are used extensively in electronic systems for frequency synthesis. Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation nonlinearity, and, in the case of phase noise cancelling fractional-N PLLs, improved phase noise cancellation. The main disadvantage of the SLF to date has been the lack of a linear time-invariant (LTI) model with which to perform the system-level design of SLF-based PLLs. Without such a model, designers are forced to rely on trial and error iteration supported by lengthy transient simulations. This paper presents an accurate LTI model of SLF-based type-II PLLs that eliminates this disadvantage.

Basic Simulation Models of Phase Tracking Devices Using MATLAB

The Phase-Locked Loop (PLL), and many of the devices used for frequency and phase tracking, carrier and symbol synchronization, demodulation, and frequency synthesis, are fundamental building blocks in today's complex communications systems. It is therefore essential for both students and practicing communications engineers interested in the design and implementation of modern communication systems to understand and have insight into the behavior of these important and ubiquitous devices. Since the PLL behaves as a nonlinear device (at least during acquisition), computer simulation can be used to great advantage in gaining insight into the behavior of the PLL and the devices derived from the PLL. The purpose of this Synthesis Lecture is to provide basic theoretical analyses of the PLL and devices derived from the PLL and simulation models suitable for supplementing undergraduate and graduate courses in communications. The Synthesis Lecture is also suitable for self study by practicing engineers. A significant component of this book is a set of basic MATLAB-based simulations that illustrate the operating characteristics of PLL-based devices and enable the reader to investigate the impact of varying system parameters. Rather than providing a comprehensive treatment of the underlying theory of phase-locked loops, theoretical analyses are provided in sufficient detail in order to explain how simulations are developed. The references point to sources currently available that treat this subject in considerable technical depth and are suitable for additional study.

A Phase-Locked Loop Model of the Response of the Postural Control System to Periodic Platform Motion

A phase-locked loop (PLL) model of the response of the postural control system to periodic platform motion is proposed. The PLL model is based on the hypothesis that quiet standing (QS) postural sway can be characterized as a weak sinusoidal oscillation corrupted with noise. Because the signal to noise ratio is quite low, the characteristics of the QS oscillator are not measured directly from the QS sway, instead they are inferred from the response of the oscillator to periodic motion of the platform. When a sinusoidal stimulus is applied, the QS oscillator changes speed as needed until its frequency matches that of the platform, thus achieving phase lock in a manner consistent with a PLL control mechanism. The PLL model is highly effective in representing the frequency, amplitude, and phase shift of the sinusoidal component of the phase-locked response over a range of platform frequencies and amplitudes. Qualitative analysis of the PLL control mechanism indicates that there is a finite range of frequencies over which phase lock is possible, and that the size of this capture range decreases with decreasing platform amplitude. The PLL model was tested experimentally using nine healthy subjects and the results reveal good agreement with a mean phase shift error of 13.7 degrees and a mean amplitude error of 0.8 mm.